TMS320F28384D: Debugging issue in Flash memory in JTAG daisy chain configuration

Hi Fabio,

I haven't seen that symbol before. What version of CCS are you using? Also, are you able to erase the flash for the second MCU using the on-chip flash tool? Can you view the contents of the flash on the second MCU in the memory browser after you connect? 

Best Regards,

Ben Collier

Hi Benjamin,

thanks for the feedback

Benjamin Collier said:

I haven't seen that symbol before.

but this is not encouraging , by the way I'm using CCS 12.5.0.00007 and CWARE 5.0.0.00 with a XDS200 debug probe.

And Yes, I'm able to erase the flash for second MCU (and also load and run the the program without "On a program load or restart" option), and I'm able to see the memory Registers in Memory Browser:

With new trials, I can add that, if I go step by step since the very beginning, I checked I got a similar 1066 error in second MCU at 

****************************************************************************
* IF _system_pre_init is 0, bypass C/C++ autoinitialization *
****************************************************************************
LCR #__system_pre_init

Moreover, I don't have anymore the strange symbol in CPU1 of the second MCU.

I want to add this: I was flashing a code with a similar linker command file:

CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start

MEMORY
{
   /* BEGIN is used for the "boot to Flash" bootloader mode   */
   BEGIN            : origin = 0x080000, length = 0x000002
   BOOT_RSVD        : origin = 0x000002, length = 0x0001AF     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x0001B1, length = 0x00024F
   RAMM1            : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD       : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD0            : origin = 0x00C000, length = 0x000800
   RAMD1            : origin = 0x00C800, length = 0x000800
   RAMLS0           : origin = 0x008000, length = 0x000800
   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
   RAMLS4           : origin = 0x00A000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800
   RAMGS0           : origin = 0x00D000, length = 0x001000
   RAMGS1           : origin = 0x00E000, length = 0x001000
   RAMGS2           : origin = 0x00F000, length = 0x001000
   RAMGS3           : origin = 0x010000, length = 0x001000
   RAMGS4           : origin = 0x011000, length = 0x001000
   RAMGS5           : origin = 0x012000, length = 0x001000
   RAMGS6           : origin = 0x013000, length = 0x001000
   RAMGS7           : origin = 0x014000, length = 0x001000
   RAMGS8           : origin = 0x015000, length = 0x001000
   RAMGS9           : origin = 0x016000, length = 0x001000
   RAMGS10          : origin = 0x017000, length = 0x001000
   RAMGS11          : origin = 0x018000, length = 0x001000
   RAMGS12          : origin = 0x019000, length = 0x001000
   RAMGS13          : origin = 0x01A000, length = 0x001000
   RAMGS14          : origin = 0x01B000, length = 0x001000
   RAMGS15          : origin = 0x01C000, length = 0x000FF8
//   RAMGS15_RSVD     : origin = 0x01CFF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   /* Flash sectors */
   FLASH0           : origin = 0x080002, length = 0x001FFE  /* on-chip Flash */
   FLASH1           : origin = 0x082000, length = 0x002000  /* on-chip Flash */
   FLASH2           : origin = 0x084000, length = 0x002000  /* on-chip Flash */
   FLASH3           : origin = 0x086000, length = 0x002000  /* on-chip Flash */
   FLASH4           : origin = 0x088000, length = 0x008000  /* on-chip Flash */
   FLASH5           : origin = 0x090000, length = 0x008000  /* on-chip Flash */
   FLASH6           : origin = 0x098000, length = 0x008000  /* on-chip Flash */
   FLASH7           : origin = 0x0A0000, length = 0x008000  /* on-chip Flash */
   FLASH8           : origin = 0x0A8000, length = 0x008000  /* on-chip Flash */
   FLASH9           : origin = 0x0B0000, length = 0x008000  /* on-chip Flash */
   FLASH10          : origin = 0x0B8000, length = 0x002000  /* on-chip Flash */
   FLASH11          : origin = 0x0BA000, length = 0x002000  /* on-chip Flash */
   FLASH12          : origin = 0x0BC000, length = 0x002000  /* on-chip Flash */
   FLASH13          : origin = 0x0BE000, length = 0x001FF0  /* on-chip Flash */
//   FLASH13_RSVD     : origin = 0x0BFFF0, length = 0x000010  /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   CPU1TOCPU2RAM   : origin = 0x03A000, length = 0x000800
   CPU2TOCPU1RAM   : origin = 0x03B000, length = 0x000800
   CPUTOCMRAM      : origin = 0x039000, length = 0x000800
   CMTOCPURAM      : origin = 0x038000, length = 0x000800

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800

   RESET            : origin = 0x3FFFC0, length = 0x000002

   CLA1_MSGRAMLOW   : origin = 0x001480,   length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500,   length = 0x000080
   CLA1_DMA_MSGRAM  : origin = 0x001680,   length = 0x000080
   DMA_CLA1_MSGRAM  : origin = 0x001700,   length = 0x000080
}

SECTIONS
{
   codestart           : > BEGIN, ALIGN(8)
   .text               : >> FLASH0 | FLASH1 | FLASH2 | FLASH3, ALIGN(8)
   .cinit              : > FLASH0 | FLASH1 | FLASH2 | FLASH3, ALIGN(8)
   .switch             : > FLASH1, ALIGN(8)
   .reset              : > RESET, TYPE = DSECT /* not used, */
   .stack              : > RAMM0 | RAMM1

#if defined(__TI_EABI__)
   .init_array      : > FLASH1, ALIGN(8)
   .bss             : > RAMLS3
   .bss:output      : > RAMLS3
   .data            : > RAMLS4
   .sysmem          : > RAMLS4
   /* Initalized sections go in Flash */
   .const           : > FLASH5, ALIGN(8)
#else
   .pinit           : > FLASH1, ALIGN(8)
   .ebss            : > RAMLS3
   .esysmem         : > RAMLS4
   /* Initalized sections go in Flash */
   .econst          : >> FLASH4 | FLASH5, ALIGN(8)
#endif

   MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
   MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
   MSGRAM_CPU_TO_CM    : > CPUTOCMRAM, type=NOINIT
   MSGRAM_CM_TO_CPU    : > CMTOCPURAM, type=NOINIT

   dclfuncs : > FLASH1, ALIGN(8)


    /* CLA specific sections */
#if defined(__TI_EABI__)
   Cla1Prog         :   LOAD = FLASH4,
                        RUN = RAMLS5,
                        LOAD_START(Cla1funcsLoadStart),
                        LOAD_END(Cla1funcsLoadEnd),
                        RUN_START(Cla1funcsRunStart),
                        LOAD_SIZE(Cla1funcsLoadSize),
                        ALIGN(8)
#else
   Cla1Prog         :   LOAD = FLASH4,
                        RUN = RAMLS5,
                        LOAD_START(_Cla1funcsLoadStart),
                        LOAD_END(_Cla1funcsLoadEnd),
                        RUN_START(_Cla1funcsRunStart),
                        LOAD_SIZE(_Cla1funcsLoadSize),
                        ALIGN(8)
#endif

   CLADataLS0       : > RAMLS0
   CLADataLS1       : > RAMLS1

   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW, type=NOINIT
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH, type=NOINIT
   Cla1ToDmaMsgRAM  : > CLA1_DMA_MSGRAM, type=NOINIT
   DmaToCla1MsgRAM  : > DMA_CLA1_MSGRAM, type=NOINIT

   Cla1DataRam      : >> RAMLS0 | RAMLS1

   /* CLA C compiler sections */
   //
   // Must be allocated to memory the CLA has write access to
   //
   CLAscratch       :
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } >  RAMLS1

   .scratchpad      : > RAMLS1
   .bss_cla         : > RAMLS1
   cla_shared       : > RAMLS1
#if defined(__TI_EABI__)
   .const_cla       :   LOAD = FLASH2,
                        RUN = RAMLS1,
                        RUN_START(Cla1ConstRunStart),
                        LOAD_START(Cla1ConstLoadStart),
                        LOAD_SIZE(Cla1ConstLoadSize)
#else
   .const_cla       :   LOAD = FLASH2,
                        RUN = RAMLS1,
                        RUN_START(_Cla1ConstRunStart),
                        LOAD_START(_Cla1ConstLoadStart),
                        LOAD_SIZE(_Cla1ConstLoadSize)
#endif


   #if defined(__TI_EABI__)
       .TI.ramfunc : {} LOAD = FLASH3,
                        RUN = RAMD0,
                        LOAD_START(RamfuncsLoadStart),
                        LOAD_SIZE(RamfuncsLoadSize),
                        LOAD_END(RamfuncsLoadEnd),
                        RUN_START(RamfuncsRunStart),
                        RUN_SIZE(RamfuncsRunSize),
                        RUN_END(RamfuncsRunEnd),
                        ALIGN(8)
   #else
       .TI.ramfunc : {} LOAD = FLASH3,
                        RUN = RAMD0,
                        LOAD_START(_RamfuncsLoadStart),
                        LOAD_SIZE(_RamfuncsLoadSize),
                        LOAD_END(_RamfuncsLoadEnd),
                        RUN_START(_RamfuncsRunStart),
                        RUN_SIZE(_RamfuncsRunSize),
                        RUN_END(_RamfuncsRunEnd),
                        ALIGN(8)
   #endif

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

I said similar, because I modified it for my trials many times, in order fix my issue... and I don't have the first one.

There is something I can try more?

Thanks,

Fabio

Fabio,

Do you remember what you were doing with the devices before you had this issue? Were you just using the blinky LED examples? 

Also, I'm curious what happens when you reset each CPU core with CCS, and then use the restart button. Do you get an error? 

Best Regards,

Ben Collier

Hi Benjamin,

I was passing from RAM debug to Flash debug of a custom code, using the linker command file or a similar one of the previous post.

Following your indications:

Benjamin Collier said:

Also, I'm curious what happens when you reset each CPU core with CCS, and then use the restart button. Do you get an error? 

It happens that MCU2 keeps resetting continuously:

and if I try to run CPU2 of MCU2, I get this:

Any idea?

Thanks,

Fabio

Hi Fabio,

Do you only have one of these custom boards? Have you tried changing your Linker CMD file to load the program into a different flash bank? 

Could you also check the data at memory location 0x78020 - 0x78026 in your memory browser? 

Best Regards,

Ben Collier

Hi Ben,

I have only one prototype of the custom board, but I tried that code in the Flash of a controlCARD with no issue. I also changed the Linker CMD file several times, now, following your suggestion I moved all the code on FLASH sectors > 8, but same issues.

This is the location you asked for in memory browser for CPU1:

this in CPU2:

Thanks again,

Fabio

Fabio,

I'll need to discuss with my coworkers about what could be causing your issue. 

Best Regards,

Ben collier

Hi Ben,

Thanks a lot, I will continue debugging in RAM, even though my code is getting larger and I always need to remap it and sometimes I have strange memory behaviour... 

Thanks again and best regards,

Fabio

Hi Ben,

any possible update from your side or anything elese could help me restore the normal behaviour of the microcontroller?

Thanks and best regards,

Fabio 

Fabio,

Our suspicion is that you are running out of HW breakpoints, since you can only use HW breakpoints in flash, while you can use software breakpoints in RAM. 

Best Regards,

Ben Collier

Fabio Rastrello said:

Till yesterday, I was able to program and debug both of them, in RAM or FLASH with no issue. 

Did anything chance between yesterday and today regarding tools versions, usage, etc? Is your environment and use case exactly the same?

Hi Ben, 

I think don't understand: can you better explain what does it mean this: 

Benjamin Collier said:

you are running out of HW breakpoints

Thanks and best regards,

Fabio

Hi Ki,

I was passing from RAM debug to Flash debug of a custom code for 2 cores in MCU2 (CPU1 and CM) and 2 cores in MCU1 (CPU1 and CPU2), that used also CLA1CPU1 for some calcs: after the issue, in my trials, I deleted the CLA code and configuration in SysConfig to simplify the project, but it did not helped. 

I can add that, in these days, also CM of MCU2 now is giving the same issue and I am forced to disable "On a program load or restart" option also for it. I don't know if it is something linked to my workspace, but I also changed it for some test and I did not see any improvement.

Thanks a lot and regards,

Fabio

Hi Ki,

thanks a lot for the clarification, but the fact is I don't have any breakpoint set: how can be something like this if I deleted all the breakpoints? Something remained in HW registers? If so, how can I restore the original behaviour?

Thanks and best regards,

Fabio

When you reproduce the issue, can you use the DEBUG_DumpBreakpoints GEL call in the scripting console and copy and paste the output to a text file and post it to this thread?

See the below post for more details on this:

https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/479091/remove-hw-breakpoint-on-ccs-v5/1733180#1733180