TMS320F28027: EPWM SOCA triggering ADC conversion too soon

Hi Mark,

A few initial questions for you:

• To clarify, are you saying the SOCA triggers as soon as you start the EPWM period (counter = 0)?
• Where does the SOCA flag of the ETFLG register get set in comparison to the value of the PWM Time Base counter? 
• Also, can I ask why you are starting with your CMPB value set to 0 instead of 500? When is the ISR called?
• If you configure the SOCAPRD bit of the ETPS register so that the SOCA occurs on the 2nd or 3rd event, do you see different behavior?

Best regards,

Allison

Hi Allison,

To answer the third question first, I am updating CMPB on each call to the EPWM ISR.  The ISR is called at TBCTR=TBPRD.

I start with SOCAPRD=1st, CMPB=0 and SOCAEN=0.

On the first ISR, I set CMPB to 500 (for example), and SOCAEN=1.  TBCTR is still incrementing.

As soon as I set CMPB to 500 (as the example) and SOCAEN=1, SOCA is triggered.  TBCTR did not reach 500 yet.

If on the 2nd ISR I leave CMPB set to 500, SOCA is triggered as expected at TBCTR = 500.

I have not tried different values of SOCAPRD.  I can do so tomorrow.

Thanks,

Mark

FYI...A couple of other things that I've tried, with no change in behavior:

At startup:

EPWM SHDWBMODE = CC_IMMEDIATE

SOCAPRD = 1st
CMPB = 0

ADC TRIGSEL=0 at start  (NEW)

ETSEL.SOCAEN=0

On first PWM ISR:

CMPB = 500

ADC.TRIGSEL = 9 (EPWM3A SOCA)

ETCLR.SOCA = 1 (NEW)

ETSEL.SOCAEN = 1

Hi Mark,

Thanks for the info and update. Could you share your EPWM configurations so I can take a look?

And how are you measuring to determine the timing of the SOC? (are you able to share some oscilloscope screenshots to show the timing of the SOC in relation to other signals?)

Best Regards,

Allison

At the rising edge of each EPWM3 pulse is an ISR ( at INTSEL = ET_CTR_PRD).   For debug, I set GPIO2 in the EPWM3 ISR.  I clear GPIO2 in the ADC ISR.  For testing, I am just setting CMPB to be duty/2, so the ISR should be in the middle of the high-time pulse.

Below is the logic capture:

You can see GPIO2 going low almost immediately on the first pulse, but goes low in the middle of the other pulses. 

At the first EPWM3 ISR, CMPB is 0 on entry, and the ISR sets this to duty/2.

I can send you the project by PM if it helps.

Thanks!

Hi Mark,

Thanks for the helpful image! Are you able to initialize CMPB to another value (e.g. 500) rather than 0 to see if this is loading-related? And yes, if you could send the configurations by PM that would work!

Best Regards,

Allison

Hi Allison,  I set CMPB to a non-zero value (which should be ~1500), and I see the same result, with the immediate trigger of the ADC ISR.   I also modified the project to disable the ADC trigger, clear the EPWM SOCA flag, ADC INT flag, with no changes.  I'll try to cut down the project to a smaller example to share.

Thanks,

Hi Allison,  

With further testing:

I have CMPA generating the EPWM interrupt, and CMPB triggering the ADC conversion, which in turn generates an interrupt.

I have both CMPA and CMPB set for IMMEDIATE load mode.

The EPWM SOCA trigger is initially disabled ETSEL.SOCAEN=0

In the CMPA ISR, I clear any SOCA flag ETCLR.SOCA=1, and then enable the SOCA trigger ETSEL.SOCAEN=1

On startup, if I have CMPA = 1500 and CMPB = 3000, I see the EPWM3/CMPA interrupt at t=1500, and then the ADC ISR interrupt (CMPB) at t=3000.  This is as expected.

On startup, if I instead have CMPA = 3000 and CMPB = 1500, on the *first PWM cycle* I see the EPWM3/CMPA interrupt at t=3000, followed immediately by the ADC ISR interrupt (CMPB) at t=3000.  This is not expected.  My expectation is that the ADC ISR interrupt would happen at t=1500 of the next PWM cycle.  After that first PWM cycle, ADC ISRs do occur at t=1500 on each new PWM cycle.

Hi Mark,

Thanks so much for the update on your findings. Since the issue seems to occur when CMPB < CMPA I'm thinking perhaps the flag from the counter hitting CMPB event isn't cleared properly so as soon as you enable the SOCA it triggers the ADC ISR. I unfortunately wasn't able to test this out today, but I will take a closer look and update tomorrow. 

Best Regards,

Allison

FYI...At startup, one of the first things I do is set PWM3 counter mode to TB_FREEZE.  When starting the pulses,  I set the mode to TB_COUNT_UP.  With a breakpoint set before setting the mode to TB_COUNT_UP, the ADC does not show a trigger flag (ADCSOCFLG1 is zero), or an overflow flag (ADCSOCOVF1 is zero), and EPWM3 ETFLG is zero.  So it looks like there should be no trigger pending for the ADC conversion.

Hi Mark,

Still reviewing the code, but thought I'd also ask if you were already referencing the ADCSOC example from C2000Ware or not - might be easier to isolate the issue using that if you want to take a look at {C2000Ware}\device_support\f2802x\examples\structs\adc_soc or implement some of the initialization where DINT; and PIE initialization occur there just to be thorough.

Another idea is could you try moving your ADC interrupt enable to later in the code (EPWM ISR)?

Best Regards,

Allison