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TMS320F28P650DK: Memory map

Rishitha
Prodigy 115 points
Part Number: TMS320F28P650DK


I've been looking into TI Example LED Blink project for dual core. In flash linker command file, We are using M0 and M1 RAM in both core 1 and core2. Then why is there same memory location for M0 and M1 RAM in both Core 1 and Core 2? Also why D2-D5 RAM address location is different for both cores?

  • 0
    TI__Mastermind 30185 points

    Hello Rishitha,

    The M0 and M1 RAM are per-CPU RAMs (see the below block diagram from the device datasheet).

    The dedicated RAM (Dx RAM) is shared between the CPUs and have a different address per the comments in the linker command file of the examples (shown below). The reason for this I'm not entirely certain, but it's likely because only 1 CPU can access those dedicated memories, and so the access is determined by the address.

  • 0 in reply to Omer Amir
    Prodigy 115 points

    What about M0 and M1, they have same address in core1 and core2. Does this mean each have two different memory blocks at same address location?

  • 0 in reply to Rishitha
    TI__Mastermind 30185 points

    Hi Rishitha,

    The diagram above indicates this, there are 2 M0/M1 RAMs, each for CPU1 and CPU2. They are different memory blocks, they are not shared by the CPUs. The memories which are shared can be seen to have both orange and blue arrows connected to their blocks.