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TMS320F28P650DK: Doubts in memory configuration

Irene Boben
Expert 1030 points
Part Number: TMS320F28P650DK

Hi team,

I have few questions regarding F28P65x memory allocation.

1. Memory 0x008000 to 0x00B999 is mentioned as can be used as CPU1 LSRAM or CLA program/data memory or D2/D3 CPU2. In the linker command file, however, it is mentioned that if we use this memory in CPU1 then we have to use 0x01A000 which is a different address. However, 0x01A000 address is mentioned as D2 RAM for CPU1 and not applicable (-) for CPU2. This is a bit confusing.

Also are there any registers which gives access control to these locations?

2. Same question as above for memory 0x00C000 to 0x00F999

3. Memory 0x004000 to 0x007999 is mentioned as LS8-9(Cla1 Program memory) and Peripherals for CPU1 and CPU2. Does this mean the peripherals mentioned can read and write from these address? I need more clarity on the peripherals memory.

Thanks and regards,

Irene

  • 0
    TI__Guru** 113105 points

    Hi,

    Irene Boben said:
    1. Memory 0x008000 to 0x00B999 is mentioned as can be used as CPU1 LSRAM or CLA program/data memory or D2/D3 CPU2. In the linker command file, however, it is mentioned that if we use this memory in CPU1 then we have to use 0x01A000 which is a different address. However, 0x01A000 address is mentioned as D2 RAM for CPU1 and not applicable (-) for CPU2. This is a bit confusing.

    There are different blocks of RAMs. LS0..LS7 which only exist for CPU1 and CLA and D2 and D3 which can be mapped to CPU1 or CPU2. When D2 and D3 are mapped to CPU2, CPU2 can access these RAM blocks in same address range as LS0..LS7. When D2 and D3 are mapped to CPU1, CPU1 can access them in address range from 0x1A000 to 0x1DFFF.

    Irene Boben said:
    Also are there any registers which gives access control to these locations?

    Please check the definition of MCUCNF1 register.

    Irene Boben said:
    3. Memory 0x004000 to 0x007999 is mentioned as LS8-9(Cla1 Program memory) and Peripherals for CPU1 and CPU2. Does this mean the peripherals mentioned can read and write from these address? I need more clarity on the peripherals memory.

    No, it just means CPU1 and CPU1 access specific peripherals in that address range where as CLA access LS8 and LS9 memory block.

    Regards,

    Vivek Singh