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TMS320F280049C: How SRAM ECC is calculated

Ben Qin
Intellectual 2685 points
Part Number: TMS320F280049C

Hi Team,

There's an issue from the customer need your help:

According to the reference manual, 32-bit data can be split into two 16-bit ECC codes to calculate two 7-bit ECC codes, and ask for help how the algorithm calculates. The ECC calculations I searched for were all 16-bit data that could calculate 5-bit ECC codes, so why do I need 7 bits?

But if I use the SECDED algorithm, I only need 5 bits of ECC to verify 16 bits of data, so why do I need 7 bits?

And I used the purchased 280049c board to test the M1, used the CCS tool to MemCfgRegs.DxTEST.bit.TEST_M1=2, and then according to the address map described in the user manual, I can read out that the corresponding ECC code is 0xC when the corresponding data is 0. How is this calculated?

Best Regards,

Ben

  • 0
    TI__Mastermind 30180 points

    Hello Ben,

    From what I could find, the ECC doesn't follow the usual hamming algorithm (per this thread), but I need to do some more research. I'll talk with some other experts and try to get back to you before the end of the week.

  • 0 in reply to Omer Amir
    TI__Mastermind 30180 points

    Hi Ben,

    Apologies for the extended delay, based on my discussion with another expert the use of 5-bit ECC over 7-bit ECC is not based on anything in particular, 5 bits are necessary but that is just the minimum, 7 bits is what's implemented.

    Ben Qin said:
    And I used the purchased 280049c board to test the M1, used the CCS tool to MemCfgRegs.DxTEST.bit.TEST_M1=2, and then according to the address map described in the user manual, I can read out that the corresponding ECC code is 0xC when the corresponding data is 0. How is this calculated?

    This information isn't readily available, what is the issue the customer is actually seeing? Are they getting unexpected ECC errors being triggered? The customer doesn't need the method of calculation for the ECC to be able to use the ECC on this device.