TMS320F280039C: EPG interrupt flag clearing

Hello Kevin,

On the interupt: it looks like your code clears the DONE and FILL flags but does not clear the global interrupt flag.

EPG_clearInterruptFlag(EPG_INT_GLOBAL_INT | EPG_INT_SIGGEN0_DONE | EPG_INT_SIGGEN0_FILL);

This should clear the interrupt flags correctly.

I am consulting with our design team to attempt to confirm if the DMA initiator has access to EPG registers. I will revert once I have more information.

Best regards,
Ibukun

The DMA does not have access to the EPG registers. The block diagram is incorrect in this regard; I am filing a ticket to have this fixed in the documentation.

I have made some updates to the code including clearing the EPG_INT_GLOBAL_INT and I am still not able to get the interrupt flags to behave as I would expect.

This is my initialization code now. I have modified it to write 60 bits at a time out of the EPG.

    EPG_selectEPGOutput(EPG1_BASE, EPG_OUT0, EPG_OUT_SEL_SIG);
    EPG_selectSignalOutput(EPG1_BASE, EPG_OUT0, EPG_SIGGEN0_DATATRANOUT0);

    // Bit period is 1.25us and there are three periods per bit. 120 MHz sysclk / 49 = 2.45 MHz
    // which gets pretty close.
    EPG_setClkGenPeriod(EPG1_BASE, EPG_CLKGEN0, 49U);

    EPG_selectSigGenClkSource(EPG1_BASE, EPG_SIGGEN0, EPG_CLKGEN0_CLKOUT0_GCLK);

    EPG_setClkGenOffset(EPG1_BASE, EPG_CLKGEN0, 0, 0);

    EPG_setDataBitLen(EPG1_BASE, EPG_SIGGEN0, 60);
    EPG_setSignalGenMode(EPG1_BASE, EPG_SIGGEN0, EPG_SIGGEN_MODE_SHIFT_RIGHT_REPEAT);

    EPG_enableGlobal(EPG1_BASE);
    EPG_enableSignalGen(EPG1_BASE, EPG_SIGGEN0);

    Interrupt_enable(INT_SYS_ERR);
    EPG_enableInterruptFlag(EPG1_BASE, EPG_INT_SIGGEN0_DONE);

My trigger code that runs every 100ms is

    data_counter = 1;

    EPG_clearInterruptFlag(EPG1_BASE, EPG_INT_SIGGEN0_FILL | EPG_INT_SIGGEN0_DONE | EPG_INT_GLOBAL_INT);
    SysCtl_clearInterruptStatus(SYSCTL_SYS_ERR_INT_CLR_GINT | SYSCTL_SYS_ERR_INT_CLR_EPG1_INT);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);

    EPG_setData0Word(EPG1_BASE, EPG_SIGGEN0, ws2812_data[0] & 0xFFFFFFFF);
    EPG_setData1Word(EPG1_BASE, EPG_SIGGEN0, ws2812_data[0] >> 32);

and my ISR is:

__interrupt void ws2812_isr(void)
{
    GPIO_writePin(21, 1);
    uint32_t epg_int_status = EPG_getInterruptStatus(EPG1_BASE);


    if (epg_int_status & EPG_INT_SIGGEN0_DONE) {
        if (data_counter < 4) {
            EPG_setData0Word(EPG1_BASE, EPG_SIGGEN0, ws2812_data[data_counter] & 0xFFFFFFFF);
            EPG_setData1Word(EPG1_BASE, EPG_SIGGEN0, ws2812_data[data_counter] >> 32);
        }
        data_counter += 1;
    }

    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
    SysCtl_clearInterruptStatus(SYSCTL_SYS_ERR_INT_CLR_GINT | SYSCTL_SYS_ERR_INT_CLR_EPG1_INT);
    EPG_clearInterruptFlag(EPG1_BASE, EPG_INT_SIGGEN0_FILL | EPG_INT_SIGGEN0_DONE | EPG_INT_GLOBAL_INT);
    GPIO_writePin(21, 0);
}

I have connected a logic analyzer to a GPIO pin that I am toggling every time the ISR runs and it appears that the ISR is running way more than it should:

Every blip of the red signal is the ISR running while the orange is the output of the EPG. It is still looking like the EPG interrupts are either not clearing or are immediately re-triggering. Is this an issue with how I am clearing the interrupt flags or is this an issue with the EPG configuration?

Hello Kevin,

I will need to look into this a little bit more, and I will revert shortly.

Thanks,
Ibukun

Hi Ibukun,

Have you gotten any more info on this?

Thanks,

Kevin

Hi Kevin,

Did a little more research here. For SYS_ERR interrupts, the source flag must be cleared before clearing GINT. In your EPG interrupt handler (SYS_ERR handler I assume), you clear GINT first, then you clear the EPG flag. This would cause GINT to be set again immediately and prevent new interrupts from being fired.

Best regards,
Ibukun

Hi Ibukun,

I have rearranged the interrupt clears as shown below:

__interrupt void ws2812_isr(void)
{
    GPIO_writePin(21, 1);
    uint32_t epg_int_status = EPG_getInterruptStatus(EPG1_BASE);


    if (epg_int_status & EPG_INT_SIGGEN0_DONE) {
        if (data_counter < 4) {
            EPG_setData0Word(EPG1_BASE, EPG_SIGGEN0, ws2812_data[data_counter] & 0xFFFFFFFF);
            EPG_setData1Word(EPG1_BASE, EPG_SIGGEN0, ws2812_data[data_counter] >> 32);
        }
        data_counter += 1;
    }

    EPG_clearInterruptFlag(EPG1_BASE, EPG_INT_SIGGEN0_FILL | EPG_INT_SIGGEN0_DONE | EPG_INT_GLOBAL_INT);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
    SysCtl_clearInterruptStatus(SYSCTL_SYS_ERR_INT_CLR_GINT | SYSCTL_SYS_ERR_INT_CLR_EPG1_INT);
    GPIO_writePin(21, 0);
}

With this change, I am still seeing the interrupts fire when they are not supposed to. I was able to change some things around so that we are disabling the interrupts when they are not needed so I have gotten this working for my application. I still think there is something not quite right going on with the interrupts continuously firing though.

Hello Kevin,

You have the EPG SIGGEN configured in SHIFT_RIGHT_REPEAT mode. In this mode, every time the signal generator finishes shifting out the length of bits configured, the DONE signal goes high and the interrupt is fired, and the pattern starts again. This happens continuously.

If you don't want the pattern shifted out continuously, then you should change the MODE to SHIFT_RIGHT_ONCE, and then you set SIGGEN_CTL0.EN to 1 when you want it to shift out.

If you want it shifted out continuously, but you don't want the interrupt to fire at the end of every BITLENGTH bits, then you need a different interrupt source (e.g. CPU Timer). If you use the EPG interrupt in repeat mode, it will always fire the interrupt every BITLENGTH clock cycles as long as EN = 1.

Does this help?

Best regards,
Ibukun

Hi Ibukun,

I think that makes sense, couple of clarifying questions:

Since I am attempting to send multiple successive writes to the SIGGEN_DATA register and then stop after those writes until it is initiated again, should I be using SHIFT_RIGHT_REPEAT for every transfer except the last one or should it be in SHIFT_RIGHT_ONCE for all of them?

I want the behavior to be it shifts out as long as I keep writing in new data and then it stops shifting once no new data is written.

Thanks,

Kevin

Ok, that all makes sense and explains the behavior that I am seeing. Sounds like the approach I am using of keeping it in repeat mode and disabling the interrupts when I don't want to feed more data is the best we can do. The last bit is always 0 for this so the repeated sending of that is not a problem for this application.

Thanks so much for the help on this!