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TMS320F28388D: The TMU question.

Luke Chen
Expert 4860 points
Part Number: TMS320F28388D

Hi champs,

In TRM, we can see a table introduces TMU Supported Instructions, there are pipeline cycles at the end of each instruction.

I am wondering how to explain this table, how many clock cycles are needed for TMU to execute those instructions respectively?

Regards,

Luke

  • 0
    TI__Mastermind 21290 points

    Luke, for example, if it's 4p, it means it takes 4 cycles to execute, but other non-conflicting instructions can be used to fill up the 3 pipeline slots.

    Thanks,

    Sira

  • 0 in reply to Sira Rao80
    TI__Expert 4860 points

    Sria,

    Thanks for your response, here are more questions need your comments,

    1. Do you mean TMU need 5 clock cycles to execute instruction DIVF32 RaH, RbH, RcH?
    2. In that table it shows the pipeline cycles of instruction MPY2PIF32 RaH, RbH is 2/3, what does it mean?
    3. What's the reason we don't use clock cycles, but use pipeline cycles instead?

    Regards,

    Luke

  • +1 in reply to Luke Chen
    TI__Mastermind 21290 points

    Luke,

    1. Yes

    2. As stated

    Instruction takes 2 pipeline cycles to execute if followed by either SINPUF32, COSPUF32 or MOV32 mem, Rx operations and 3 pipeline cycles for all other operations (FPU or TMU).

    3. It is referring to Clock cycles, but it's pointing out the fact that the pipeline slots can either be NOPs or filled with some other (allowed) instructions.

    Thanks,

    Sira