• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 83 subscribers
  • Views 162 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280039C: Response time from CMPSS detection to EPWM trip taking action for OCP/OVP

Johnny Chen
Expert 4450 points
Part Number: TMS320F280039C

Tool/software:

Hi Champ,

I am asking for my customer.

In general, OCP and OVP protection are normally using CMPSS to detect for implementation, then if the event occurs, signal is connected to the ePWM X-BAR for ePWM trip response.

Checking on the total response time from CMPSS detection to EPWM trip taking action for OCP/OVP protection.

(1). Is it step response time (21~60ns) for CMPSS Response time parameter + td(TZ-PWM) + the parasitic load on the EPWM pin ? Any parameter missing here ?

(2). From customer's observation of testing the OCP on their own board, it takes about 20ms which ns should be a reasonable timing at here. What could be the possible issues here ?

CH1: PWM output ; CH2: OCP PIN trigger signal

Thanks and regards,

Johnny

  • +1
    TI__Genius 14131 points

    Hi Johnny,

    What frequency is the customer running their device clock at, specifically the EPWM clock? 20 ms is much too long response time for OCP/OVP if they are utilizing the CMPSS + EPWM trip zone. 

    For fastest response, CTRIPH/CTRIPL should be configured to come from the asynchronous input. The only other source of delay is coming from the EPWM which has 3 TBCLK cycle latch time to register trip signal from CMPSS. If TBCLK is configured as divided from the device SYSCLK, this can lead to elongation of trip timinig.

    Regards,

    Peter