TMS320F28388D: MCAN Debug

Hi Lawrence,

When they send a sequence of messages from a Peak PCAN-USB FD Adapter to the TI F28388D MCAN device we see consistent but random message losses

Do these messages have the same message ID? The received messages can be stored in RX buffers, or RX FIFOs. There are separate interrupts for RX buffer and RX FIFO. Have you enabled both the interrupts?

Can you share the MCAN configurations including the timing parameters in your project?

Hi QJ,

Will share MCAN code Debug report seperately 

The Testing report is

1. Based on the ex1 and ex2 configuration
2. What they see:  missing data and more data at the same time when interface other driver .
3. There is no issue when interface with TI example(send by ex2 modification to send sequence data)
4. Additional information: minimum modification on ex10 by only add the size of the receive buffer, the same issue.

Answer to your questions

1. The messages have the same Message ID as there is just the single Master and the Slave which is the TI.
2. They believe they have enabled both interrupts, please check the code for specifics and whether the implementation is correct.
3. They are running at CAN FD speed of 1Mbps nominal and 1Mbps data.

 Regards,

Lawrence

Hi QJ,

The customer is running 1Mbit ID, and 1Mbit Data.  The limitation is they are using SN65HVD230 in the setup, that my understanding does not support CAN FD higher speed. 

Not sure if thats the issue or not but can you run at 1Mbit ID and 1Mbit Data?

Regards,

Lawrence

Hi QJ,

Update from customer:

>>> What is the cycle time for PCAN to transmit message repeatedly? 

I have been trying from the range of 1ms to 10s as cycle time to send a sequence of messages.

>>> When running the test with cycle time = 20ms, and haven't produced any issue.

I got the similar result which is the total message count is good, but the received message content is not as expected.

From previous report, I sent an “sawtooth message” in a sequence (as figure below), in the cycle time of 10s. (I manually sent each message), the observation is the total message count is correct, however the message is not as the sent message.

In addition, could you use the MCAN ex1 or ex2 configuration to run the test? Since we are using the MCAN module on ARM core which we can directly try the configuration if yours is working.

QJ,

Thanks. Can you provide your test code?

Regards,

Lawrence

QJ,

Also the customer is saying they are manually communicating to F28388D so the cycle time is around 10 seconds.  So something else is going on.

Regards,

Lawrence

Hi Lawrence,

sure, I will upload my test code.

Hi QJ,

Feedback from the customer in regards to your project:

Could you explain more about what the project is about? And it seems not what we want from the previous response.

• The fdMore and brsEnable are both “0”, it is the classic CAN operation NOT the CANFD?
• It is only having 1 message in the rxMsg buffer, our major issue is the sequential receiving is not working.(Please refer to the report that attached)
• I load the project and I send message with Std ID of 0x4h but doesn’t receive and message and not triggering the interrupt.

I have the original ex4 project and modify to the setup , I can see it receive data and but I can see a lot of error generated in the interrupt function. I suspect the sampling point percentage is not right.

Could you provide the instruction of configuring the nominal and data segment of sampling in percentage?

Such as the code below, what is the sample point in percentage?

    //

    // Initialize bit timings.

    // =40MHz/[(1+1)*(14+3+3)] = 1Mbps

    bitTimes.nomRatePrescalar   = 0x1U; // Nominal Baud Rate Pre-scaler

    bitTimes.nomTimeSeg1        = 14U; // Nominal Time segment before SP

    bitTimes.nomTimeSeg2        = 0x3U; // Nominal Time segment after SP

    bitTimes.nomSynchJumpWidth  = 0x3U; // Nominal SJW

    // =40MHz/[(0+1)*(14+3+3)] = 1Mbps

    bitTimes.dataRatePrescalar  = 0x1U; // Data Baud Rate Pre-scaler

    bitTimes.dataTimeSeg1       = 14U; // Data Time segment before SP

    bitTimes.dataTimeSeg2       = 3U; // Data Time segment after SP

    bitTimes.dataSynchJumpWidth = 3U; // Data SJW

//

Can you support a call with the customer as this getting very urgent.

Regards,

Lawrence

Hi Lawrence,

It is ex4 with minor changes. 

1. Regular CAN is used: fdMore=0 and brsEnable=0

2. The PCAN keeping transmitting one message (ID=4) every 1ms.

3. F28 CAN is in interrupt mode, and is waiting for the message in a while() loop

4. The GPIO18 and GPIO19 are used for CAN

5. The 20MHz crystal is used 

Hi QJ,

Any update on the code example for using a memory buffer in the ARM code for MCAN-Receive/ex2 example?

Regards,

Lawrence

Additional question from the customer:

======================

Thank you for the detailed information. I am already familiar with the filter and SFT setup in the example. What I am specifically looking for is clarification on the functions used within the interrupt function, as well as the sequence in which these functions should be called. This is critical for ensuring that our implementation is correct.

Could you please provide more insight into the function calls and their sequence within the interrupt context?

 =====================

Regards,

Lawrence

Hi QJ,

From Customer:

=============

Thank you for the detailed insights into the interrupts and exceptions. However, to ensure we can implement the MCAN code correctly and efficiently, we would feel much more confident if we had a working reference example that specifically handles interrupt functions within the interrupt context.

This example is particularly critical for us as many future products will rely on this MCAN code. Having a clear reference will not only help us but also ensure that our implementation is robust and reliable.

Could you please provide an example that includes the sequence of function calls within the interrupt service routines (ISR), particularly focusing on how to handle interrupts within those functions? Your support in providing this would be greatly appreciated.

Thank you in advance for your continued assistance

=============

Regards,

Lawrence

The SW team is taking care of the questions from Lawrence.

Hi QJ,

Feedback from customer:

=============

Thank you for sharing the provided example. Upon reviewing it, I noticed that, aside from changes in the bit timing configuration, there don't appear to be any other updates compared to the official mcan_ex2_external_loopback example.

What I specifically need help with is understanding which functions I should call within the receive ISR and the correct sequence for handling incoming messages when using the memory buffer to receive. This information is crucial for us to ensure that the ISR behaves correctly in our application.

 ============

Any guidance on this?

Regards,

Lawrence

Thank you for your detailed explanation regarding the interrupt handling sequence for the MCAN core. I have a few follow-up points and requests:

1. The setup you provided seems to focus on the handling process for CPU1  ( references to  the mcan_ex4_receive example). However, we need the version that operates on the ARM core. Could you please provide that?

2. My main/original concern is with the functions MCAN_ClearLineInterrupt() and MCAN_ClearACKGroup(), which you mentioned "must be cleared manually." These functions do not appear to exist in the MCAN library, and this could present a major issue for our program's implementation. Could you clarify if these functions are part of a different module or if there are alternative functions we should be using to manually clear interrupts, especially in the context of the ARM core?

3. Could you please provide a working example that demonstrates receiving messages using the memory buffer and the corresponding ISR function calls? A brief explanation of the sequence would also be greatly appreciated, especially how it should be implemented for our scenario.

Yes, I can do it.

Hi QJ,

Any update? Customer requesting a meeting to discuss this need.

Regards,

Lawrence

Hi Lawrence,

McAN_ClearACKGroup() should be Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9) which is API of C2000ware.

MCAN_ClearLineInterrupt() is MCAN_clearInterrupt() in C2000ware

The MCAN interrupts should be handled in the same procedure for C28 and CM.For CM, the Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9) is not needed.

The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at the end of the ISR. If the PIEACK bit is not cleared, the CPU does not receive any further interrupts from that group. This does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.

QJ,

Customer still need some clarification regarding your latest response:

 ============================

You mentioned,

>>> 

"When CM enters the ISR, the state of the interrupt is changed from pending to active. For a level-sensitive interrupt, when CM returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the CM to immediately re-enter the ISR. So we need to clear the interrupt status and clear the line interrupt."

I would greatly appreciate it if you could provide a complete working example demonstrating the correct handling of receiving messages using the memory buffer, including the sequence of ISR function calls, particularly in relation to clearing the interrupt status and line interrupt as mentioned. A step-by-step explanation would be very helpful to ensure proper implementation in our scenario.

We have a session scheduled for tomorrow morning, and hopefully, we can use that opportunity to clarify any confusion. As this has now been going back and forth for 4 weeks, a clear example would help us finally move forward.

===================

Regards,

Lawrence

Hi Lawrence,

Nice having a meeting with customer. Attached is the example used in the meeting:

MCAN_Receive_RxBuff_FIFO_F28388_CortexM4.zip