TMS320F280025C: ISR doesn't work after PWR reset but works when upload and disconnecting JTAG probe

Additional clue:

I use Uniflash to flash .out file into MCU, to bypass the CCS setup bifurcation.

Interesting things happened:

1. I load the .out file to MCU, ISR works.

2. I shutdown the device and reboot, the ISR not work -> This makes sense, it happened as I use CCS to debug.

3. Move to Uniflash, I hit Reset Actions -> System Reset (or CPU reset) -> Reset Now

4. The ISR works!

Also, use XRSn pin to reset the device, the ISR will not work.

Hope this can help

Hi Chun-lin,

Chun-Lin Chen said:

2. Is the linked command file I use is correct?

Yes these files that you have are the correct ones.

Regarding the ISR issue, let me ask a colleague on this as this may be related to boot mode, JTAG/Emulation issue.

Best,

Ryan Ma

Hi Chun-Lin,

Can you confirm if the boot mode pins are properly set up for Flash boot? Can you verify that the watchdog is disabled in code_start?

Just so I understand what you have done so far:

1. You're able to view the GPIO toggle when booting from Flash?

2. When JTAG is connected you're unable to view any GPIO toggling?

Best,

Ryan Ma

Thanks, I can exclude the linker cmd file issue.

Hi, Ryan:

The GPIO32 is connect to GPIO33 then through 10kOhm pull-up to 3V3.

and GPIO2 is also a pull-up then connect to 3V3.

for your question:

1. I also toggle another GPIO32 in Timer2 ISR, the GPIO works fine when I give it a full power cycle which disconnect the JTAG and boot from flash.

But only the EMWP1 TZ ISR can not trigger the GPIO4. I had confium the GPIO4 is MUXed to GPIO function.

2. When JTAG is connect, I can view the GPIO toggling, also unplug the connector. But when I shutdown the device and turn-on again, the EPWM1 TZ ISR didn't work anymore.

3. For the watchdog question, I connect the JTAG and execute single step, it execute DisableDog() function in f28002x_sysctrl.c, the f28002x_sysctrl.c full file is as follows:

//###########################################################################
//
// FILE:   f28002x_sysctrl.c
//
// TITLE:  f28002x Device System Control Initialization & Support Functions.
//
// DESCRIPTION:  Example initialization of system resources.
//
//###########################################################################
//
//
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "f28002x_device.h"     // Headerfile Include File
#include "f28002x_examples.h"   // Examples Include File

//
// Functions that will be run from RAM need to be assigned to a different
// section.  This section will then be mapped to a load and run address using
// the linker cmd file.
//
//      *IMPORTANT*
//
//  IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM
//  FLASH TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM
//  THROWING AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE.
//
#pragma CODE_SECTION(InitFlash, ".TI.ramfunc");
#pragma CODE_SECTION(FlashOff, ".TI.ramfunc");


// The following values are used to validate PLL Frequency using DCC
//
#define   DCC_COUNTER0_TOLERANCE   1

//
// Macro used for adding delay between 2 consecutive writes to CLKSRCCTL1
// register.
// Delay = 300 NOPs
//
#define SYSCTRL_CLKSRCCTL1_DELAY  asm(" RPT #250 || NOP \n RPT #50 || NOP")

//
// To use INTOSC as the clock source, comment the #define USE_PLL_SRC_XTAL,
// and uncomment the #define USE_PLL_SRC_INTOSC
//
//#define USE_PLL_SRC_XTAL
#define USE_PLL_SRC_INTOSC

#define _FLASH

//
// InitSysCtrl - Initialization of system resources.
//
void InitSysCtrl(void)
{
    //
    // Disable the watchdog
    //
    DisableDog();

#ifdef _FLASH
    //
    // Copy time critical code and Flash setup code to RAM. This includes the
    // following functions: InitFlash()
    //
    // The  RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart
    // symbols are created by the linker. Refer to the device .cmd file.
    //
    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

    //
    // Call Flash Initialization to setup flash waitstates. This function must
    // reside in RAM.
    //
    InitFlash();
#endif

    //
    // Initialize the SYSPLL control  to generate a 200Mhz clock
    //
    // Defined options to be passed as arguments to this function are defined
    // in f28002x_examples.h.
    //
    // Note: The internal oscillator CANNOT be used as the PLL source if the
    // PLLSYSCLK is configured to frequencies above 194 MHz.
    //
    //  PLLSYSCLK = (XTAL_OSC) * (IMULT) /(REFDIV) * (ODIV) * (PLLSYSCLKDIV)
    //
#if defined(USE_PLL_SRC_XTAL)
    InitSysPll(XTAL_OSC, IMULT_30, REFDIV_2, ODIV_3, PLLCLK_BY_1, SYSCTL_DCC_BASE0);
#elif defined(USE_PLL_SRC_INTOSC)
    InitSysPll(INT_OSC2, IMULT_30, REFDIV_1, ODIV_3, PLLCLK_BY_1, SYSCTL_DCC_BASE0);
#endif

#ifndef _FLASH
    //
    // Call Device_cal function when run using debugger
    // This function is called as part of the Boot code. The function is called
    // in the InitSysCtrl function since during debug time resets, the boot code
    // will not be executed and the gel script will reinitialize all the
    // registers and the calibrated values will be lost.
    //
    Device_cal();
#endif

    //
    // Turn on all peripherals
    //
    InitPeripheralClocks();
}

//
// InitPeripheralClocks - Initializes the clocks for the peripherals.
//
// Note: In order to reduce power consumption, turn off the clocks to any
// peripheral that is not specified for your part-number or is not used in the
// application
//
void InitPeripheralClocks(void)
{
    EALLOW;

    CpuSysRegs.PCLKCR0.bit.DMA = 1;
    CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
    CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1;
    CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1;
    CpuSysRegs.PCLKCR0.bit.HRCAL = 1;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    CpuSysRegs.PCLKCR0.bit.CPUBGCRC = 1;

    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM5 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM6 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM7 = 1;

    CpuSysRegs.PCLKCR3.bit.ECAP1 = 1;
    CpuSysRegs.PCLKCR3.bit.ECAP2 = 1;
    CpuSysRegs.PCLKCR3.bit.ECAP3 = 1;

    CpuSysRegs.PCLKCR4.bit.EQEP1 = 1;
    CpuSysRegs.PCLKCR4.bit.EQEP2 = 1;

    CpuSysRegs.PCLKCR7.bit.SCI_A = 1;

    CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
    CpuSysRegs.PCLKCR8.bit.SPI_B = 1;

    CpuSysRegs.PCLKCR9.bit.I2C_A = 1;

    CpuSysRegs.PCLKCR10.bit.CAN_A = 1;

    CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
    CpuSysRegs.PCLKCR13.bit.ADC_C = 1;

    CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1;
    CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1;
    CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1;
    CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1;

    CpuSysRegs.PCLKCR19.bit.LIN_A = 1;
    CpuSysRegs.PCLKCR19.bit.LIN_B = 1;

    CpuSysRegs.PCLKCR20.bit.PMBUS_A = 1;

    CpuSysRegs.PCLKCR21.bit.DCC0 = 1;
    CpuSysRegs.PCLKCR21.bit.DCC1 = 1;

    EDIS;
}

//
// DisablePeripheralClocks - Gates-off all peripheral clocks.
//
void DisablePeripheralClocks(void)
{
    EALLOW;

    CpuSysRegs.PCLKCR0.all = 0;
    CpuSysRegs.PCLKCR2.all = 0;
    CpuSysRegs.PCLKCR3.all = 0;
    CpuSysRegs.PCLKCR4.all = 0;
    CpuSysRegs.PCLKCR7.all = 0;
    CpuSysRegs.PCLKCR8.all = 0;
    CpuSysRegs.PCLKCR9.all = 0;
    CpuSysRegs.PCLKCR10.all = 0;
    CpuSysRegs.PCLKCR13.all = 0;
    CpuSysRegs.PCLKCR14.all = 0;
    CpuSysRegs.PCLKCR19.all = 0;
    CpuSysRegs.PCLKCR20.all = 0;
    CpuSysRegs.PCLKCR21.all = 0;

    EDIS;
}

//
// InitFlash - This function initializes the Flash Control registers.
//
//      *CAUTION*
// This function MUST be executed out of RAM. Executing it out of OTP/Flash
// will yield unpredictable results.
//
#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#endif
void InitFlash(void)
{
    EALLOW;

    //
    // At reset bank and pump are in sleep. A Flash access will power up the
    // bank and pump automatically.
    //
    // Power up Flash bank and pump. This also sets the fall back mode of
    // flash and pump as active.
    //
    Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1;
    Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3;

    //
    // Disable Cache and prefetch mechanism before changing wait states
    //
    Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0;
    Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0;

    //
    // Set waitstates according to frequency
    //
    //      *CAUTION*
    // Minimum waitstates required for the flash operating at a given CPU rate
    // must be characterized by TI. Refer to the datasheet for the latest
    // information.
    //
#if CPU_FRQ_100MHZ
        Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x4;
#endif

    //
    // Enable Cache and prefetch mechanism to improve performance of code
    // executed from Flash.
    //
    Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1;
    Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1;

    //
    // At reset, ECC is enabled. If it is disabled by application software and
    // if application again wants to enable ECC.
    //
    Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;

    EDIS;

    //
    // Force a pipeline flush to ensure that the write to the last register
    // configured occurs before returning.
    //
    __asm(" RPT #7 || NOP");
}

//
// FlashOff - This function powers down the flash
//
//      *CAUTION*
// This function MUST be executed out of RAM. Executing it out of OTP/Flash
// will yield unpredictable results. Also you must seize the flash pump in
// order to power it down.
//
#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#endif
void FlashOff(void)
{
    EALLOW;

    //
    // Power down bank
    //
    Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0;

    //
    // Power down pump
    //
    Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0;

    EDIS;
}


//
// ServiceDog - This function resets the watchdog timer.
//
// Enable this function for using ServiceDog in the application.
//
void ServiceDog(void)
{
    EALLOW;
    WdRegs.WDKEY.bit.WDKEY = 0x0055;
    WdRegs.WDKEY.bit.WDKEY = 0x00AA;
    EDIS;
}

//
// DisableDog - This function disables the watchdog timer.
//
void DisableDog(void)
{
    volatile Uint16 temp;

    //
    // Grab the clock config first so we don't clobber it
    //
    EALLOW;
    temp = WdRegs.WDCR.all & 0x0007;
    WdRegs.WDCR.all = 0x0068 | temp;
    EDIS;
}

//
// InitPll - This function initializes the PLL registers.
//
// Note: This function uses the DCC to check that the PLLRAWCLK is running at
// the expected rate. The desirable DCC can be provided as a parameter.
//
void InitSysPll(Uint16 clock_source, Uint16 imult, Uint32 refdiv, Uint32 odiv,
                 Uint16 divsel, Uint32 dccbase)
{
    Uint32 timeout,temp_syspllmult, pllLockStatus;
    bool status;

    if(((clock_source & 0x3) == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL)    &&
       (((clock_source & 0x4) >> 2) == ClkCfgRegs.XTALCR.bit.SE)           &&
       (imult  == ClkCfgRegs.SYSPLLMULT.bit.IMULT)           &&
       (refdiv  == ClkCfgRegs.SYSPLLMULT.bit.REFDIV)          &&
       (odiv == ClkCfgRegs.SYSPLLMULT.bit.ODIV)               &&
       (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV))
    {
        //
        // Everything is set as required, so just return
        //
        return;
    }

    EALLOW;

    //
    // First modify the PLL multipliers if the multipliers need an update or PLL needs
    // to be powered on / enabled
    //
    if((imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT) ||
       (refdiv != ClkCfgRegs.SYSPLLMULT.bit.REFDIV)||
       (odiv != ClkCfgRegs.SYSPLLMULT.bit.ODIV) ||
       (1U != ClkCfgRegs.SYSPLLCTL1.bit.PLLEN))
    {
        //
        // Bypass PLL and set dividers to /1
        //
        ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0;

        //
        // Delay of at least 120 OSCCLK cycles required post PLL bypass
        //
        asm(" RPT #120 || NOP");

        //
        // Evaluate PLL multipliers and dividers
        //
        temp_syspllmult = ((refdiv << 24U) | (odiv << 16U)| imult);

        //
        // Turnoff the PLL
        //
        ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0;
        EDIS;

        //
        // Delay of at least 66 OSCCLK cycles
        //
        asm(" RPT #66 || NOP");

        if(((clock_source & 0x3) != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) ||
          (((clock_source & 0x4) >> 2) != ClkCfgRegs.XTALCR.bit.SE))
        {
            switch (clock_source)
            {
                case INT_OSC1:
                    SysIntOsc1Sel();
                    break;

                case INT_OSC2:
                    SysIntOsc2Sel();
                    break;

                case XTAL_OSC:
                    SysXtalOscSel();
                    break;

                case XTAL_OSC_SE:
                    SysXtalOscSESel();
                    break;
            }
        }

        //
        // Delay of at least 60 OSCCLK cycles
        //
        asm(" RPT #60 || NOP");

        EALLOW;

        //
        // Set dividers to /1 to ensure the fastest PLL configuration
        //
        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0;

        //
        // Program PLL multipliers
        //
        ClkCfgRegs.SYSPLLMULT.all = temp_syspllmult;

        //
        // Enable SYSPLL
        //
        ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1;

        //
        // Lock time is 1024 OSCCLK * (REFDIV+1)
        //
        timeout = (1024U * (refdiv + 1U));
        pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS;

        //
        // Wait for the SYSPLL lock
        //
        while((pllLockStatus != 1) && (timeout != 0U))
        {
            pllLockStatus = ClkCfgRegs.SYSPLLSTS.bit.LOCKS;
            timeout--;
        }

        EDIS;

        //
        // Check PLL Frequency using DCC
        //
        status = IsPLLValid(dccbase, clock_source, INT_PLL_SYSPLL,
                            imult, odiv , refdiv);

    }
    else
    {
        //
        // Re-Lock of PLL not needed since the multipliers
        // are not updated
        //
        status = true;
    }

    if(status)
    {
        EALLOW;
        //
        // Set divider to produce slower output frequency to limit current increase
        //
        if(divsel != PLLCLK_BY_126)
        {
            ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1;
        }
        else
        {
            ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;
        }

        //
        // Enable PLLSYSCLK is fed from system PLL clock
        //
        ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;

        //
        // Small 100 cycle delay
        //
        asm(" RPT #100 || NOP");

        //
        // Set the divider to user value
        //
        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel;
        EDIS;
    }
    else
        ESTOP0; // If the frequency is out of range, stop here.

}

//
// SysIntOsc1Sel - This function switches to Internal Oscillator 1.
//
void SysIntOsc1Sel(void)
{
    EALLOW;
    ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2;     // Clk Src = INTOSC1
    EDIS;
}

//
// SysIntOsc2Sel - This function switches to Internal oscillator 2.
//
void SysIntOsc2Sel(void)
{
    EALLOW;
    ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0;     // Clk Src = INTOSC2
    EDIS;
}

//
// PollX1Counter - Clear the X1CNT counter and then wait for it to saturate
// four times.
//
static void
PollX1Counter(void)
{
    Uint16 loopCount = 0;

    //
    // Delay for 1 ms while the XTAL powers up
    //
    // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles
    //
    F28x_usDelay(2000);

    //
    // Clear and saturate X1CNT 4 times to guarantee operation
    //
    do
    {
        //
        // Keep clearing the counter until it is no longer saturated
        //
        while(ClkCfgRegs.X1CNT.all > 0x1FF)
        {
            ClkCfgRegs.X1CNT.bit.CLR = 1;
            ClkCfgRegs.X1CNT.bit.CLR = 0;
        }

        //
        // Wait for the X1 clock to saturate
        //
        while(ClkCfgRegs.X1CNT.all != 0x7FFU)
        {
            ;
        }

        //
        // Increment the counter
        //
        loopCount++;
    }while(loopCount < 4);
}
// SysXtalOscSel - This function switches to External CRYSTAL oscillator.
//
void SysXtalOscSel(void)
{
    EALLOW;
    ClkCfgRegs.XTALCR.bit.OSCOFF = 0;     // Turn on XTALOSC
    ClkCfgRegs.XTALCR.bit.SE = 0;         // Select crystal mode
    EDIS;

    //
    // Wait for the X1 clock to saturate
    //
    PollX1Counter();

    //
    // Select XTAL as the oscillator source
    //
    EALLOW;
    ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1;
    EDIS;

    //
    // If a missing clock failure was detected, try waiting for the X1 counter
    // to saturate again. Consider modifying this code to add a 10ms timeout.
    //
    while(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0)
    {
        EALLOW;
        ClkCfgRegs.MCDCR.bit.MCLKCLR = 1;
        EDIS;

        //
        // Wait for the X1 clock to saturate
        //
        PollX1Counter();

        //
        // Select XTAL as the oscillator source
        //
        EALLOW;
        ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1;
        EDIS;
    }
}

//
// SysXtalOscSESel - This function switches to external oscillator in
// single-ended mode and turns off all other clock sources to minimize power
// consumption. This option may not be available on all device packages
//
void
SysXtalOscSESel (void)
{
    EALLOW;
    ClkCfgRegs.XTALCR.bit.OSCOFF = 0;     // Turn on XTALOSC
    ClkCfgRegs.XTALCR.bit.SE = 1;         // Select single-ended mode
    EDIS;

    //
    // Wait for the X1 clock to saturate
    //
    PollX1Counter();

    //
    // Select XTALOSC as the oscillator source
    //
    EALLOW;
    ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1;
    EDIS;

    //
    // If missing clock detected, there is something wrong with the oscillator
    // module.
    //
    if(ClkCfgRegs.MCDCR.bit.MCLKSTS != 0)
    {
        ESTOP0;
    }
}

//
// IDLE - Enter IDLE mode
//
void
IDLE()
{
    EALLOW;
    CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE;
    EDIS;
    asm(" IDLE");
}

//
// HALT - Enter HALT mode
//
void
HALT()
{
    EALLOW;
    CpuSysRegs.LPMCR.bit.LPM = LPM_HALT;
    ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0;
    ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0;
    EDIS;
    asm(" IDLE");
}

//*****************************************************************************
//
// SysCtl_isPLLValid()
//
//*****************************************************************************
bool
IsPLLValid(Uint32 base, Uint16 oscSource, Uint16 pllclk, Uint16 imult,
           Uint16 odiv, Uint16 refdiv)
{
    float fclk1_0ratio;
    volatile struct DCC_REGS *DccRegs;

    EALLOW;

    //
    // Assigning DCC for PLL validation
    // Enable Peripheral Clock Domain PCLKCR21 for DCC
    //
    if(base == SYSCTL_DCC_BASE0)
    {
            DccRegs = &Dcc0Regs;
            CpuSysRegs.PCLKCR21.bit.DCC0 = 1;
    }
    else if(base == SYSCTL_DCC_BASE1)
    {
            DccRegs = &Dcc1Regs;
            CpuSysRegs.PCLKCR21.bit.DCC1 = 1;
    }
    else
        ESTOP0; // Invalid DCC selected

    //
    // Clear Error & Done Flag
    //
    DccRegs->DCCSTATUS.bit.ERR = 1;
    DccRegs->DCCSTATUS.bit.DONE = 1;

    //
    // Disable DCC
    //
    DccRegs->DCCGCTRL.bit.DCCENA = 0x5;

    //
    // Disable Error Signal
    //
    DccRegs->DCCGCTRL.bit.ERRENA = 0x5;

    //
    // Disable Done Signal
    //
    DccRegs->DCCGCTRL.bit.DONEENA = 0x5;

    //
    // Configure Clock Source1 to PLL
    //
    // Clk Src1 Key 0xA to enable clock source selection
    //
    switch(pllclk)
    {
        case INT_PLL_SYSPLL:
            DccRegs->DCCCLKSRC1.all = 0xA000; // Clk Src1 = SYSPLL
            break;

        default:
            //
            // Code shouldn't reach here
            //
            break;
    }

    //
    // Configure Clock Source0 to whatever is set as a reference
    // clock source for PLL
    //
    // Clk Src0 Key 0xA to enable clock source selection
    //
    switch(oscSource)
    {
        case INT_OSC1:
            DccRegs->DCCCLKSRC0.all = 0xA001; // Clk Src0 = INTOSC1
            break;

        case INT_OSC2:
            DccRegs->DCCCLKSRC0.all = 0xA002; // Clk Src0 = INTOSC2
            break;

        case XTAL_OSC:
        case XTAL_OSC_SE:
            DccRegs->DCCCLKSRC0.all = 0xA000; // Clk Src0 = XTAL
            break;

        default:
            //
            // Code shouldn't reach here
            //
            break;
    }

    //
    // Calculating frequency ratio of output clock(f1) vs reference clock(f0)
    //
    fclk1_0ratio = (float)imult / ((odiv + 1U) * (refdiv + 1));

    //
    // Computing and configuring Counter0 , Counter1 & Valid Seed Values
    // with +/-1% tolerance for the desired DCC
    //
    ComputeCntrSeedValue(base, fclk1_0ratio, DCC_COUNTER0_TOLERANCE);

    //
    // Enable Single Shot Mode
    //
    DccRegs->DCCGCTRL.bit.SINGLESHOT = 0xA;

    //
    // Enable DCC to start counting
    //
    DccRegs->DCCGCTRL.bit.DCCENA = 0xA;
    EDIS;

    //
    // Wait until Error or Done Flag is generated
    //
    while((DccRegs->DCCSTATUS.all & 3) == 0)
    {
    }

    //
    // Returns true if DCC completes without error
    //
    return((DccRegs->DCCSTATUS.all & 3) == 2);

}

//*****************************************************************************
//
// ComputeCntSeedValid - Compute Counter seed values based on the frequency ratio of output
// clock vs reference clock & tolerance expected for the desired DCC
//
//*****************************************************************************
void ComputeCntrSeedValue(Uint32 base, float fclk1_0ratio, Uint32 tolerance)
{
    Uint32 window, dccCounterSeed0, dccValidSeed0, dccCounterSeed1, total_error;
    volatile struct DCC_REGS *DccRegs;

    if(fclk1_0ratio >= 1U)
     {
        //
        // Setting Counter0 & Valid Seed Value with expected tolerance
        // Total error is 12
        //
        window = (12U * 100U) / tolerance;
        dccCounterSeed0 = window - 12U;
        dccValidSeed0 = 24U;

     }
    else
     {
        total_error = (((Uint32)2U / fclk1_0ratio) + (Uint32)10U);

        window = ((total_error * 100U)/ tolerance);

        //
        // Setting Counter0 & Valid Seed Value with expected tolerance
        //
        dccCounterSeed0 = window - total_error;
        dccValidSeed0 = (Uint32)2U * total_error;

     }

    //
    // Multiplying Counter-0 window with PLL Integer Multiplier
    //
    dccCounterSeed1 = window * fclk1_0ratio;

    //
    // Assigning DCC for PLL validation
    //
    if(base == SYSCTL_DCC_BASE0)
        DccRegs = &Dcc0Regs;
    else if(base == SYSCTL_DCC_BASE1)
        DccRegs = &Dcc1Regs;
    else
        ESTOP0; // Invalid DCC selected

    //
    // Configure COUNTER-0, COUNTER-1 & Valid Window
    //
    DccRegs->DCCCNTSEED0.bit.COUNTSEED0 = dccCounterSeed0; // Loaded Counter0 Value
    DccRegs->DCCVALIDSEED0.bit.VALIDSEED = dccValidSeed0;  // Loaded Valid Value
    DccRegs->DCCCNTSEED1.bit.COUNTSEED1 = dccCounterSeed1; // Loaded Counter1 Value
}

//
// End of File
//

I check the f28002x_codestartbranch.asm is no modified, the full file is as follows:

;//###########################################################################
;//
;// FILE:   f28002x_codestartbranch.asm
;//
;// TITLE: Branch for redirecting code execution after boot.
;//
;// For these examples, code_start is the first code that is executed after
;// exiting the boot ROM code.
;//
;// The codestart section in the linker cmd file is used to physically place
;// this code at the correct memory location. This section should be placed
;// at the location the BOOT ROM will re-direct the code to. For example,
;// for boot to FLASH this code will be located at 0x80000.
;//
;// In addition, the example f28002x projects are setup such that the codegen
;// entry point is also set to the codestart label. This is done by linker
;// option -e in the project build options. When the debugger loads the code,
;// it will automatically set the PC to the "entry point" address indicated by
;// the -e linker option. In this case the debugger is simply assigning the PC,
;// it is not the same as a full reset of the device.
;//
;// The compiler may warn that the entry point for the project is other then
;//  _c_init00. _c_init00 is the C environment setup and is run before
;// main() is entered. The codestart code will re-direct the execution
;// to _c_init00 and thus there is no worry and this warning can be ignored.
;//
;//###########################################################################
;//
;//
;// $Copyright:
;// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
;//
;// Redistribution and use in source and binary forms, with or without 
;// modification, are permitted provided that the following conditions 
;// are met:
;// 
;//   Redistributions of source code must retain the above copyright 
;//   notice, this list of conditions and the following disclaimer.
;// 
;//   Redistributions in binary form must reproduce the above copyright
;//   notice, this list of conditions and the following disclaimer in the 
;//   documentation and/or other materials provided with the   
;//   distribution.
;// 
;//   Neither the name of Texas Instruments Incorporated nor the names of
;//   its contributors may be used to endorse or promote products derived
;//   from this software without specific prior written permission.
;// 
;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;// $
;//###########################################################################

***********************************************************************

WD_DISABLE  .set  1    ;set to 1 to disable WD, else set to 0

    .ref _c_int00
    .global code_start

***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************

    .sect "codestart"
    .retain

code_start:
    .if WD_DISABLE == 1
        LB wd_disable       ;Branch to watchdog disable code
    .else
        LB _c_int00         ;Branch to start of boot._asm in RTS library
    .endif

;end codestart section

***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
    .if WD_DISABLE == 1

    .text
wd_disable:
    SETC OBJMODE        ;Set OBJMODE for 28x object code
    EALLOW              ;Enable EALLOW protected register access
    MOVZ DP, #7029h>>6  ;Set data page for WDCR register
    MOV @7029h, #0068h  ;Set WDDIS bit in WDCR to disable WD
    EDIS                ;Disable EALLOW protected register access
    LB _c_int00         ;Branch to start of boot._asm in RTS library

    .endif

;end wd_disable

    .end

;//
;// End of file.
;//

The C2000 linker "File search Path" is here, hope this can help

Also, this is how I done in my main.c

#include <custom_files.h>
#include "string.h"
#include "math.h"


//******************************************************************
// global variables
//******************************************************************
uint32_t xxx = 0;

void main(void)
{

    // Initialize device clock and peripherals
    InitSysCtrl();

    GPIO_init();
    ADC_init();
    SCI_init();
    SPI_init();
    Timer2_init();
    CMPSS_init();
    XBAR_init();
    EPWM_init();
    Interrupt_init();
    
    some_function();
	DELAY_US(50000);
	
    some_function();
	DELAY_US(50000);
	
    some_function();
	xxx = 0;

	while(1){
		// Do nothing
	}
}

additional infomation:

I try another F280025C device, the issue is the same.

I can provide the EPWM1 module settings and other code by mail, also If I can provide any useful information, please let me know.

Hi Chun-Lin,

What is connected to GPIO33? I am wondering if this is affecting the boot mode in some way.

Chun-Lin Chen said:

The C2000 linker "File search Path" is here, hope this can help

Can you remove the third row in the include library file or command file in input. This is for file search path. Instead can you directly include this file in your project?

Please try to emulate standalone boot (check BOOTROM chapter) , set a breakpoint at address 0x80000 and hit run. When you hit run, your PC should reach 0x80000. This would confirm that your boot pins configurations and hardware setup is fine for standalone boot.

Did you change your project settings to be CPU1_FLASH? Are you loading the correct .out from the CPU1_FLASH folder?

The next steps once confirmed that you're booting from the proper Flash address can be taken

Are you generating any other interrupts from the EPWM module?

Can you confirm that after a power reset, that ePWM1's TBCTR is still running running and outputting expected waveform with out the trip?

What is generating the TZISR? 

Best,

Ryan Ma

Hi, Ryan:

Thanks for your reply, I'm checking the item you mention step by step.

1. GPIO32 is directly connect to GPIO33.

2. I remove the include path and copy "28002x_generic_flash_lnk.cmd" to project folder, this bypass my original link cmd file I used (f28002x_headers_nonbios.cmd)

And the compiler report warning.

I ignore the warning and run the debug session, the progeam holt at f28002x_sysctrl.c InitSysPll() function.

The status varialbe is zero, where status is defiled by

status = IsPLLValid(dccbase, clock_source, INT_PLL_SYSPLL,
                            imult, odiv , refdiv);

tracing in , seems the DCCSTATUS register is all zero.

I use internal OSC as clock source, I define USE_PLL_SRC_INTOSC in stsctrl.c file.

Also I defined _FLASH just like above code section.

Hope this can help.

Hi Chun-lin,

Can you include the below file? I believe this is required for bitfield related projects which is why you're seeing those warnings.

Chun-Lin Chen said:

f28002x_headers_nonbios.cmd

Do the warnings go away after this?

Hi, Ryan:

Yes, the error is gone. I swap two file's include method.

I use driverlib and bitfield for this project, I defined the _DUAL_HEADERS in the linker preprocessing setup

I include the f28002x_headers_nonbios.cmd file in linker search path

In CCS general setup, I use 28002x_generic_flash_lnk.cmd for the command file.

Here is the .cproject file, I convert the file extension to .txt, Hope this can help

/cfs-file/__key/communityserver-discussions-components-files/171/3000.cproject.txt

Thanks!

Hi Chun-lin,

Instead of including it via file search path. Can you copy it in your project like they way you did it for the 28002x_generic_flash_lnk.cmd file?

You will need both .cmd files.

Chun-Lin Chen said:

2. I remove the include path and copy "28002x_generic_flash_lnk.cmd" to project folder, this bypass my original link cmd file I used (f28002x_headers_nonbios.cmd)

Try and rebuild this, and see if any behavior changes when running from Flash.

Best,

Ryan Ma

Hi, Ryan:

The setup of CCS stays the same

and I remove the cmd file from Linker file search path.

The project can build but the behavior still the same.

Can you provide some artical of how to get into emulate standalone boot?

For another PWM interrupts, I'll try use EPWM3 or EPWM4 for the TZ interrupt.

The RZ interrupt is connect to DC modula and CMPSS

The setup code is below:

/cfs-file/__key/communityserver-discussions-components-files/171/monitor_5F00_ext_5F00_card_5F00_PerInit.c

Chun-Lin Chen said:

Can you provide some artical of how to get into emulate standalone boot?

You should be able to see your code branch to 0x80000, if you're booting from FLASH. This should be the start of your main() function.

You could set up a hardware breakpoint via CCS to ensure that your application is going to that location. Or you could go to the address via the dissembly and set a breakpoint there.

Can you confirm the application is able to branch to the main?

Best,

Ryan Ma

Hi, Ryan:

The code can branch to the main after launch.

I got my code branch from 0x80000

Then in 0x83840 is wd_disable function, then CAN successfully go into main function.

Is there any method can do debug but not load the progran to MCU?

Thanks!

Hi Chun-lin,

Okay so it seems it's booting correctly from Flash.

Can you now verify by adding a hardware breakpoint to where the TZ interrupt is occurring and seeing if that breakpoint is being reached? If it is being reached, can you disconnect the JTAG, and do a power cycle on the device. The behavior should stay the same if your boot pins are correct and being pulled high.

Do you see the GPIO toggle in the TZ interrupt after doing a power cycle of device?

To debug and not load the program to MCU, you can load a symbol instead. To load the symbol it would be loading the same .out. 

Best,

Ryan Ma

Hi, Ryan:

I add HW breakpoint inside the breakpoint view in CCS as follow, ISR can be reached.

After disconnect JTAG and a power cycle, the program can not reach ISR anymore.

But other ISR (like Timer2ISR) which flashing another LED can still work.

Here is the waveform of VDD(1V2), GPIO24, GPIO32 and XRS pin.

To load the symbol without loading program, I can not connect to target from debug mode, the option is gray.

I need to hit the bug icon to debug and load the program, then disconnect target, thenI can select the "load symbol" option.

And after connect the target and load symbol, the program stop at "ESTOP".

But I think this is another topic, We can keep on finding the solution of the ISR issue.

I'll try use another PWM module, please kindly wait my experiment.

Thanks

Chun-Lin Chen said:

I need to hit the bug icon to debug and load the program, then disconnect target, thenI can select the "load symbol" option.

Hi Chun-lin,

Try the following:

1. Create a target configuration file or re use the one you're currently using. To view this tab in the screenshot, go to View -> TargetConfigurations.

You should see your project, and the target configuration file associated with it.

2. Right click on the target configuration file, and select "Launch Selected Configuration"

3. Then right click and connect to target.

4. Then load the symbols.

Best,

Ryan Ma

Hi, Ryan:

For using the method you provide, the program still hit the ESTOP instruction.

But I think I found the solution of the ISR issue.

I should enable the TZ ISR after my interrupt initial process, otherwise the ISR can not reset by reseting EPwm1Regs.TZCLR

The following debug process I do is:

1. I disable the TZ ISR, focuseing to the TZ event, and assign GPIO as PWM output. I check if the TZ event happened when UVLO CMPSS is been triggered -> The EPWM trip function works correctly, same as I reboot the device.

2. I enable the ISR again, after a power cycle, the EPWM pin state stuck at the trip event, which means it can not generate the PWM signal.

Even the CMPSS should not generate the TZ event anymore, the PWM output still stays at the trip state.(TZ_FORCE_HI or TZ_FORCE_LO)

3. I move the code" EPwm1Regs.TZEINT.bit.OST    = TZ_ENABLE;" after interrupt interrupt initial process, the code works well and PWM can be generate correctly.

The exact location of the code can refer to following code.

void main(void)
{

    // Initialize device clock and peripherals
    InitSysCtrl();

    GPIO_init();
    ADC_init();
    SCI_init();
    SPI_init();
    Timer2_init();
    CMPSS_init();
    XBAR_init();
    EPWM_init();
    Interrupt_init();

	EALLOW;
    EPwm1Regs.TZEINT.bit.OST    = TZ_ENABLE;    // Enable OST interrupt
    EDIS;
    
    ...
    
}

And this is what I do inside the Interrupt_Init() function

void Interrupt_init()
{
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;

    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    InitPieVectTable();

    // Interrupt setup

    EALLOW;
    PieVectTable.ADCA1_INT  = &ADCINT1_ISR;
    PieVectTable.EPWM1_TZ_INT = &Epwm1_TZ_ISR;
    PieVectTable.TIMER2_INT = &Timer2_ISR;
    PieVectTable.SCIA_RX_INT = &SCIA_RXFIFO_ISR;
    PieVectTable.SCIA_TX_INT = &SCIA_TXFIFO_ISR;


    PieCtrlRegs.PIEIER1.bit.INTx1 = 1;  // INT1.1 ADCINT A1
    PieCtrlRegs.PIEIER2.bit.INTx1 = 1;  // INT2.1 EPWM1 TZ
    PieCtrlRegs.PIEIER8.bit.INTx13 = 1; // INT8.13 PMBUSA
    PieCtrlRegs.PIEIER9.bit.INTx1 = 1;  // INT9.1 SCIA_RX
    PieCtrlRegs.PIEIER9.bit.INTx2 = 1;  // INT9.2 SCIA_TX

    IER |= M_INT1;  // Enable group 1 interrupt (ADCA1)
    IER |= M_INT2;  // Enable group 2 interrupt (EPWM1 TZ)
    IER |= M_INT8;  // Enable group 8 interrupt (PMBUSA)
    IER |= M_INT9;  // Enable group 9 interrupt (SCIA_RX, SCIA_TX)
    IER |= M_INT14; // Enable group 14 interrupt (Timer2)

    // Write a 0 to this bit to clear it to 0 and clear the interrupt request
    IFR = 0x0000;

    // Writing 1 to the respective interrupt bit clears the bit and enables the PIE block
    PieCtrlRegs.PIEACK.bit.ACK1 = 1;
    PieCtrlRegs.PIEACK.bit.ACK2 = 1;
    PieCtrlRegs.PIEACK.bit.ACK4 = 1;
    PieCtrlRegs.PIEACK.bit.ACK8 = 1;
    PieCtrlRegs.PIEACK.bit.ACK9 = 1;

    CpuTimer2Regs.TCR.bit.TRB = 1; // Reload CPUtimer2
    CpuTimer2Regs.TCR.bit.TSS = 0; // start timer2
    CpuTimer2Regs.TCR.bit.TIF = 1; // Clear timer overflow flag
    CpuTimer2Regs.TCR.bit.TIE = 1; // Enable CPU-Timer Interrupt

    // kick start all interrupt peripherals

    EDIS;

    EINT; // Enable Global interrupt INTM
    ERTM; // Enable Global real time interrupt DBGM
}

Is there any sequence to setup the TZ and TZ ISR, so I can avoid this situation next time?

Thanks for the help, and above information also help alot!

Hi Chun-lin,

The sequence to set up the TZ and TZ ISR or the ePWM in general usually goes like the following

1. Initialize PWM (Do not start TBCLKSYNC yet)

2. Initialize PIE interrupt

3. Start PWM when ready

However, one thing I noticed in the initialization that I would like for you to experiment with.

InitSysCtrl(); 

This function is being called first and will initialize your device clock and enable clock to all peripherals. There is a specific one related to the ePWM called TBCLKSYNC. 

Can you disable this in the InitSysCtrl() by setting TBCLKSYNC = 0, only after you set up your ePWM and ready to start your PWM, can you set the TBCLKSYNC = 1? TBCLKSYNC starts your ePWM counter of all PWMs.

See if that helps with this issue.

Best,

Ryan Ma

Hi, Ryan:

Ryan Ma said:

Can you disable this in the InitSysCtrl() by setting TBCLKSYNC = 0, only after you set up your ePWM and ready to start your PWM, can you set the TBCLKSYNC = 1? TBCLKSYNC starts your ePWM counter of all PWMs.

I tried these solution, and neigher of them can not fix the issue.

1. I remove the line CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; and enable the TZEINT.bit.OST = TZ_ENABLE again in EPWM_init().

I set CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; in InitPeripheralClocks() which inside InitSysCtrl()

void InitPeripheralClocks(void)
{
    EALLOW;

    CpuSysRegs.PCLKCR0.bit.DMA = 1;
    CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
    CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1;
    CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1;
    CpuSysRegs.PCLKCR0.bit.HRCAL = 1;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    CpuSysRegs.PCLKCR0.bit.CPUBGCRC = 1;

    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM5 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM6 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM7 = 1;

    CpuSysRegs.PCLKCR3.bit.ECAP1 = 1;
    CpuSysRegs.PCLKCR3.bit.ECAP2 = 1;
    CpuSysRegs.PCLKCR3.bit.ECAP3 = 1;

    CpuSysRegs.PCLKCR4.bit.EQEP1 = 1;
    CpuSysRegs.PCLKCR4.bit.EQEP2 = 1;

    CpuSysRegs.PCLKCR7.bit.SCI_A = 1;

    CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
    CpuSysRegs.PCLKCR8.bit.SPI_B = 1;

    CpuSysRegs.PCLKCR9.bit.I2C_A = 1;

    CpuSysRegs.PCLKCR10.bit.CAN_A = 1;

    CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
    CpuSysRegs.PCLKCR13.bit.ADC_C = 1;

    CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1;
    CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1;
    CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1;
    CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1;

    CpuSysRegs.PCLKCR19.bit.LIN_A = 1;
    CpuSysRegs.PCLKCR19.bit.LIN_B = 1;

    CpuSysRegs.PCLKCR20.bit.PMBUS_A = 1;

    CpuSysRegs.PCLKCR21.bit.DCC0 = 1;
    CpuSysRegs.PCLKCR21.bit.DCC1 = 1;

    EDIS;
}

And then set  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; inside the Interrupt_Init(), which is the last step for the initialial process and after EPWM_Init() function.

At this time, the EPWM should start after all the setup and PIE setup.

void Interrupt_init()
{
    ...
    
    CpuTimer2Regs.TCR.bit.TRB = 1; // Reload CPUtimer2
    CpuTimer2Regs.TCR.bit.TSS = 0; // start timer2
    CpuTimer2Regs.TCR.bit.TIF = 1; // Clear timer overflow flag
    CpuTimer2Regs.TCR.bit.TIE = 1; // Enable CPU-Timer Interrupt

    // kick start all interrupt peripherals
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;            // EPWM time base clock sync release

    EDIS;

    EINT; // Enable Global interrupt INTM
    ERTM; // Enable Global real time interrupt DBGM
}

But the result is the same, PWM output pin state is TZ_FORCE_LO after a power cycle.

2. I recover the  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; inside InitPeripheralClocks()

And the result in the same, it also can't work.

The ideal behavior should like this, TZ GPIO toggle(red) after MCU start(blue) and before Vout stable(green).

Otherwise if the function doesn't work, the red and yellow stays low.

Thanks.

Hi Chun-lin,

The image you have is the ideal behavior correct? And the configuration you had to follow was enable the TZEINT after you've initialized your device, and peripherals correct?

In the incorrect configuration can you diff between the working configuration of the ePWM registers and the non working ePWM registers?

Best,

Ryan Ma

Hi, Ryan:

Left side is the solution code, right side is the code have issue.

Note that EPwm1Regs.TZSEL.bit.DCAEVT2 is enable or not doesn't effect the behavior.

And te main.c difference is

Hope this help!

Thanks

Hi Chun-Lin,

Thank you for the diff, will need to confirm with team member on this interrupt configuration. I will be OOO today, but will be back on Monday. Apologize for the delay in response.

Best,

Ryan Ma

Hi Chun-Lin,

I am in training all week and will not be able to test this myself.

But I did have a question.

When does the TZ Flag OSHT bit get set? Does it get set before PWM initialization? If so, have you made sure to clear the TZ flags before starting the PWM during initalization?

Best,

Ryan MA

Hi, Rayn:

I check the epwm register, the TZFLG only set after initial process.

I only clear the TZCLR.bit.OST inside wpem init, but not all TZ events.

Then I try to clear all TZ events, the result is the same.

Thanks!

Hi Chun-lin,

Thank you for verifying, could you package me a test case that demonstrates what you're seeing for both enabling TZ interrupt after interrupt initialization and before initialization? The two behaviors, where one works and one does not.

If you can strip down all other code that is not relevant that would be great.

Best

Ryan Ma

Hi, I organize the files and hope this can help.

/cfs-file/__key/communityserver-discussions-components-files/171/PWM_5F00_TZ_5F00_ISR_5F00_Issue.zip

Hi Chun-lin,

I am able to build the project and will run the test case. Thank you.

Best,

Ryan Ma

Thanks, this worked! 

Is there any other official material mention this expect example code?

Hi Chun-lin,

I am sure there are official material that mention this. However I am not sure where it is specifically located... 

Best,

Ryan Ma