TMS320F28035-EP: EPWM4 CMPA trigger multiple ADC conversions

Gregory Helton

Part Number: TMS320F28035-EP

Tool/software:

I've spend several hours trying to find out why my EPWM4 CMPA interrupt is not triggering a series of ADC conversions (SOC1,2,3,4,5. In fact, it's triggering none as witnessed by ADCINTFLG.

I can set a breakpoint at the EPWM4 interrupt, and it is firing as expected. So there must be something with either the EPWM4 configuration or SOC setups.

The goal is to trigger SOC1, SOC2, SOC3, SOC4, and SOC5 from the EPWM4 CMPA event. TBCTR is counting up. When ADCINT4 occurs (triggered by EOC3), then I will read ADCRESULT1,2,3. ADCRESULT4,5 will be read later.

EPWM4 is setup to trigger SOCA and SOCB (code below)

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    //*************************************************
    // Configure ePWM4 module
    // We don't generate PWM with this one.
    //
    // PWM Period = 66.67uS, 15KHZ
    // Count Up mode
    // Set PWM output on Zero
    // Clear on CMPA, CMPB compare
    // TBCLK = 15MHZ (66.67nS resolution)
    // CMPA triggers an ADC SOCA and SOCB event on
    // first pulse.
    //************************************************
    EPwm4Regs.TBPRD = 1000;                             // Period = 1000 TBCLK counts (1000 x 66.67nS = 66.67uS)  was 1799 GAH
    EPwm4Regs.CMPA.half.CMPA = 50;                     // Compare A = 50 TBCLK counts
    EPwm4Regs.CMPB = 50;                               // Compare B = 50 TBCLK counts
    EPwm4Regs.TBPHS.all = 0;                            // Set Phase register to zero
    EPwm4Regs.TBCTR = 0;                                // clear TB counter
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;             // Phase loading disabled
    EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    //*************************************************
    // Configure ePWM4 module
    // We don't generate PWM with this one.
    //
    // PWM Period = 66.67uS, 15KHZ
    // Count Up mode
    // Set PWM output on Zero
    // Clear on CMPA, CMPB compare
    // TBCLK = 15MHZ (66.67nS resolution)
    // CMPA triggers an ADC SOCA and SOCB event on
    // first pulse.
    //************************************************

    EPwm4Regs.TBPRD = 1000;                             // Period = 1000 TBCLK counts (1000 x 66.67nS = 66.67uS)  was 1799 GAH
    EPwm4Regs.CMPA.half.CMPA = 50;                     // Compare A = 50 TBCLK counts
    EPwm4Regs.CMPB = 50;                               // Compare B = 50 TBCLK counts
    EPwm4Regs.TBPHS.all = 0;                            // Set Phase register to zero
    EPwm4Regs.TBCTR = 0;                                // clear TB counter
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;             // Phase loading disabled
    EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;

    EPwm4Regs.TBCTL.bit.CLKDIV = 0;                     // 0 = CLKDIV = 1
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = 2;                  // 2 = HPCLKDIV = 4
                                                        // TBCLK = SYSCLKOUT / (HPCLKDIV * CLKDIV)
                                                        // TBLCK = 60MHZ / ( 4 * 1) = 15MHZ

    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;       // load on CTR = Zero
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;       // load on CTR = Zero

    EPwm4Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;            // No action on Compare A zero
    EPwm4Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;            // No action on Compare A match
    EPwm4Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;            // No action on Compare B zero
    EPwm4Regs.AQCTLB.bit.CBU = AQ_NO_ACTION;            // No action on Compare B match


    EPwm4Regs.ETSEL.bit.SOCAEN = 1;                     // Enable EPWM4SOCA pulse
    EPwm4Regs.ETSEL.bit.SOCBEN = 1;                     // Enable EPWM4SOCB pulse
    EPwm4Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPA;         // EPWM4SOCA pulse when TBCTR = CMPA while incrementing.
    EPwm4Regs.ETSEL.bit.SOCBSEL = ET_CTRU_CMPA;         // EPWM4SOCB pulse when TBCTR = CMPA while incrementing.

    EPwm4Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA;          // EPWM4 TBCTR = CMPA while counting up causes interrupt
    EPwm4Regs.ETSEL.bit.INTEN = 0;                      // EPWM4INT disabled (enabled later)

    EPwm4Regs.ETPS.bit.SOCAPRD = ET_1ST;                // EPWM4SOCA pulse on first event
    EPwm4Regs.ETPS.bit.SOCBPRD = ET_1ST;                // EPWM4SOCB pulse of first event
    EPwm4Regs.ETPS.bit.INTPRD = ET_1ST;                 // Interrupts enabled

ADC SOC setup code

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    //*******************************************
    // SOC1,2,3,4 and 5 are triggered by ePWM4
    // CMPA event for measuring:
    // SOC1 - I_MOTOR
    // SOC2 - I_OFF
    // SOC3 - VBUS,
    // SOC4 - 3V3,
    // SOC5 - TEMPERATURE (INTERNAL)
    // These have the  next highest priority after
    // SOC0. ADC conversions will occur in
    // round-robin order once triggered, starting
    // at SOC1.
    //********************************************
    //************************************
    // SOC1
    // ADCINT2
    // ADCTRIG11, EPWM4, ADCSOCA
    // ADCINA2, Motor Current, CH2
    // Sample Window = 6 (7), 233nS
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    //*******************************************
    // SOC1,2,3,4 and 5 are triggered by ePWM4
    // CMPA event for measuring:
    // SOC1 - I_MOTOR
    // SOC2 - I_OFF
    // SOC3 - VBUS,
    // SOC4 - 3V3,
    // SOC5 - TEMPERATURE (INTERNAL)
    // These have the  next highest priority after
    // SOC0. ADC conversions will occur in
    // round-robin order once triggered, starting
    // at SOC1.
    //********************************************


    //************************************
    // SOC1
    // ADCINT2
    // ADCTRIG11, EPWM4, ADCSOCA
    // ADCINA2, Motor Current, CH2
    // Sample Window = 6 (7), 233nS
    //
    // ADCINT2 pulses generated when EOC1
    // ADCINT2 enabled
    // EOC1 is trigger for ADCINT2
    //************************************

    AdcRegs.ADCSOC1CTL.bit.CHSEL = 2;                   // ADCINA2, I_MOT, CH2
    AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 11;                // ADCTRIG11, ePWM4, ADCSOCA
    AdcRegs.ADCSOC1CTL.bit.ACQPS = 6;                   // (6 + 1) x 33.33nS = 233.3 nS

    AdcRegs.INTSEL1N2.bit.INT2CONT = 1;                 // ADCINT2 pulses generated every EOC1 event
    AdcRegs.INTSEL1N2.bit.INT2E = 1;                    // ADCINT2 enabled
    AdcRegs.INTSEL1N2.bit.INT2SEL = 1;                  // EOC1 is trigger for ADCINT2



    //************************************
    // SOC2
    // ADCINT3
    // ADCTRIG11, EPWM4, ADCSOCA
    // ADCINA1, I_OFF, CH1
    // Sample Window = 6 (7), 233nS
    //
    // ADCINT3 pulses generated when EOC2
    // ADCINT3 enabled
    // EOC2 is trigger for ADCINT3
    //************************************

    AdcRegs.ADCSOC2CTL.bit.CHSEL = 1;                   // ADCINA1, I_OFF, CH2
    AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 11;                // ADCTRIG11, ePWM4, ADCSOCA
    AdcRegs.ADCSOC2CTL.bit.ACQPS = 6;                   // (6 + 1) x 33.33nS = 233.3 nS

    AdcRegs.INTSEL3N4.bit.INT3CONT = 1;                 // ADCINT3 pulses generated every EOC2 event
    AdcRegs.INTSEL3N4.bit.INT3E = 1;                    // ADCINT3 enabled
    AdcRegs.INTSEL3N4.bit.INT3SEL = 2;                  // EOC2 is trigger for ADCINT3


    //************************************
    // SOC3
    // ADCINT4
    // ADCTRIG12, EPWM4, ADCSOCB
    // ADCINB1, VBUS, CH9
    // Sample Window = 6 (7), 233nS
    //
    // ADCINT4 pulses generated when EOC3
    // ADCINT4 enabled
    // EOC3 is trigger for ADCINT4
    //************************************

    AdcRegs.ADCSOC3CTL.bit.CHSEL = 9;                   // ADCINB1, VBUS, CH9
    AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 12;                // ADCTRIG12, ePWM4, ADCSOCB
    AdcRegs.ADCSOC3CTL.bit.ACQPS = 6;                   // (6 + 1) x 33.33nS = 233 nSec

    AdcRegs.INTSEL3N4.bit.INT4CONT = 1;                 // ADCINT4 pulses generated every EOC3 event
    AdcRegs.INTSEL3N4.bit.INT4E = 1;                    // ADCINT4 enabled
    AdcRegs.INTSEL3N4.bit.INT4SEL = 3;                  // EOC3 is trigger for ADCINT4



    //************************************
    // SOC4
    // ADCINT5
    // ADCTRIG12, EPWM4, ADCSOCB
    // ADCINB2, 3V3
    // Sample Window = 6 (7), 233nS
    //
    // ADCINT5 pulses generated when EOC4
    // ADCINT5 enabled
    // EOC4 is trigger for ADCINT5
    //************************************

    AdcRegs.ADCSOC4CTL.bit.CHSEL = 10;                 // ADCINB2, 3V3, CH10
    AdcRegs.ADCSOC4CTL.bit.TRIGSEL = 12;               // ADCTRIG12, ePWM4, ADCSOCB
    AdcRegs.ADCSOC4CTL.bit.ACQPS = 6;                  // (6 + 1) x 33.33nS = 233 nSec

    AdcRegs.INTSEL5N6.bit.INT5CONT = 1;                 // ADCINT5 pulses generated every EOC4 event
    AdcRegs.INTSEL5N6.bit.INT5E = 1;                    // ADCINT5 enabled
    AdcRegs.INTSEL5N6.bit.INT5SEL = 4;                  // EOC4 is trigger for ADCINT5



    //************************************
    // SOC5
    // ADCINT6
    // ADCTRIG11, EPWM4, ADCSOCA
    // ADCINA5 (Internal), TEMPERATURE
    // Sample Window = 6 (7), 233nS
    //
    // ADCINT6 pulses generated when EOC5
    // ADCINT6 enabled
    // EOC5 is trigger for ADCINT6
    //************************************

    AdcRegs.ADCSOC5CTL.bit.CHSEL = 5;                   // ADCINA5 (Internal), TEMPERATURE, CH5
    AdcRegs.ADCSOC5CTL.bit.TRIGSEL = 11;                // ADCTRIG11, ePWM4, ADCSOCA
    AdcRegs.ADCSOC5CTL.bit.ACQPS = 6;                   // (6 + 1) x 33.33nS = 233 nSec

    AdcRegs.INTSEL5N6.bit.INT6CONT = 1;                 // ADCINT6 pulses generated every EOC4 event
    AdcRegs.INTSEL5N6.bit.INT6E = 1;                    // ADCINT6 enabled
    AdcRegs.INTSEL5N6.bit.INT6SEL = 5;                  // EOC5 is trigger for ADCINT6

I have setup EPWM4 to generate ADCSOCA and ADCSOCB pulses since some of the channels are on ADCINA and some are on ADCINB.

Any help would be appreciated.

Thanks

-----------------------------------------------------------

Additional Information

Checking the EPWM4 ETFLG register, I can see that SOCA and SOCB have been triggered, in addition to the INT flag (register value = 0x000D) This is captured with a breakpoint set at EPWM4 ISR.

But when I look at the ADCINTFLG register (value = 0x0000) is see that no conversions have been completed.

Now you might say that no conversions have had time to complete yet, so no flags will be set (yet). But if I continue to single set out of the interrupt, and continue to step for a long time afterward, no ADCINTFLG ever gets set.

It appears, that at least for EPWM4, that the SOCA and SOCB flags are not triggering ADC conversions.

Also, here is the rest of the ADC initialization code.

You can see that SOCPRIORITY = 1, which sets SOC0 as highest priority, and SOC1-15 are in round robin mode.

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  //***************************************************
    // ADC Configuration
    //
    // ADC external reference
    // Reference buffers on
    // ADC Powered Up
    // ADC Enabled
    //
    // BandGap circuit powered on
    //
    // ADC result latched 1 cycle prior to result
    // VREFLO internally connected to ADC for sampling
    // Temperature sensor connected internally to ADCINA5
    //****************************************************
    AdcRegs.ADCCTL1.bit.ADCREFSEL = 1;                  // ADC External references
    AdcRegs.ADCCTL1.bit.ADCPWDN = 1;                    // ADC power on
    AdcRegs.ADCCTL1.bit.ADCREFPWD = 1;                  // reference buffer on
    AdcRegs.ADCCTL1.bit.ADCBGPWD = 1;                   // band-gap powered on  (MUST BE ON FOR ADC TO WORK)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  //***************************************************
    // ADC Configuration
    //
    // ADC external reference
    // Reference buffers on
    // ADC Powered Up
    // ADC Enabled
    //
    // BandGap circuit powered on
    //
    // ADC result latched 1 cycle prior to result
    // VREFLO internally connected to ADC for sampling
    // Temperature sensor connected internally to ADCINA5
    //****************************************************

    AdcRegs.ADCCTL1.bit.ADCREFSEL = 1;                  // ADC External references

    AdcRegs.ADCCTL1.bit.ADCPWDN = 1;                    // ADC power on
    AdcRegs.ADCCTL1.bit.ADCREFPWD = 1;                  // reference buffer on
    AdcRegs.ADCCTL1.bit.ADCBGPWD = 1;                   // band-gap powered on  (MUST BE ON FOR ADC TO WORK)

    AdcRegs.ADCCTL1.bit.ADCENABLE = 1;                  // ADC Enabled

    AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1;                // INT pulse 1 cycle before ADC result latched
    AdcRegs.ADCCTL1.bit.VREFLOCONV = 1;                 // VREFLO connected internally to ADC
    AdcRegs.ADCCTL1.bit.TEMPCONV = 1;                   // temperature sensor connected to ADCINA5 internally

    AdcRegs.SOCPRICTL.bit.SOCPRIORITY = 1;              // SOC0 highest, SOC1-15 round robin


    //***********************************************
    // No overlap of sample and conversion
    // ADCCLK = SYSCLK/2 (30MHZ)
    //***********************************************

    AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1;              // No overlap of sample and conversion
    AdcRegs.ADCCTL2.bit.CLKDIV2EN = 1;                  // ADCCLK = 30MHZ

Any comments ?

8 months ago

0 Benjamin Collier 8 months ago

TI__Mastermind 33116 points

Hi,

Gregory Helton said:
I've spend several hours trying to find out why my EPWM4 CMPA interrupt is not triggering a series of ADC conversions (SOC1,2,3,4,5. In fact, it's triggering none as witnessed by ADCINTFLG.

Are you seeing any change in your ADC results registers? Maybe the interrupt is setup incorrectly. I do not see your code to register or enable the interrupt.

Thanks,

Ben Collier

0 Gregory Helton 8 months ago in reply to Benjamin Collier

Intellectual 370 points

Although it shows that I have interrupts enabled in the SOC setups, I do not have the PIE interrupt enabled for these conversions. Instead, I poll the ADCINTFLG register for conversion complete, then clear the flag(s). I do see some stuff in two of the ADCRESULT registers, but I think it's valid data, just leftovers. No ADCINTFLG was ever set.

0 Benjamin Collier 8 months ago in reply to Gregory Helton

TI__Mastermind 33116 points

Gregory,

Just to confirm, do you see the ADCINT flag being set if you use the AdcRegs.ADCSOCFRC1 register to force a conversion?

Thanks,

Ben Collier

0 Gregory Helton 8 months ago in reply to Benjamin Collier

Intellectual 370 points

Yes. After a manual SW trigger of SOC1-SOC5 using ADCSOCFRC1, ADCINTFLG = 0x3E, and ADCRESUL1-5 has valid (expected) data.

0 Gregory Helton 8 months ago in reply to Benjamin Collier

Intellectual 370 points

Additional information.

I am still unclear as to whether or not I need to trigger both SOCA and SOCB for round-robbin SOC setups on ADC conversions that span channels across ADCINAx and ADCINBx. Do I need to set the SOC trigger for ADCSOCA on SOC setups that are to convert channels located on ADCINA, and ADCSOCB on SOC setups that are to convert channels on ADCINB ?

ADCSOCxCTL has triggers (ADCTRIG11 for ADCSOCA on EPWM4, and ADCTRIG12 for ADCSOCB on EPWM4).

I've tried setting the SOC triggers to only ADCTRIG11 for all of the round-robin channels. In addition, I've tried setting SOC triggers to either ADCTRIG11 for ADCINA channels, and ADCTRIG12 for ADCINB channels. All with the same result - no conversions triggered.

In addition, I've tried enabling SOCAEN only in the EWPM4 config. AND both SOCAEN and SOCBEN in ETSEL. Still, no ADC triggers as far as I can tell.

The ETFLG register for EPWM4 indicates that a SOC pulse has been sent. This screen snapshot shows an example of an SOCAEN only test. It can be seen that the SOCA flag is set along with the INT flag, but no indication of an ADCINTFLG (polled).

There is every indication that there is some sort of a disconnect between the SOC pulses from the EPWM4 module and the SOC input(s) to the ADC. Manually forcing SOCx on the ADC starts conversions just fine. On the PWM side, the ETFLG says it has sent the SOC pulse, but no conversion has started/completed. I've looked at this from just about every angle, and I just don't see the problem.

0 Benjamin Collier 8 months ago in reply to Gregory Helton

TI__Mastermind 33116 points

Gregory,

I will try to get back to you this week, but I am out of office for the next few days.

Best Regards,

Ben Collier

0 Benjamin Collier 8 months ago in reply to Benjamin Collier

TI__Mastermind 33116 points

Gregory,

For some reason, I did not think that we had any example with EPWM triggering the ADC SOCs, but I was incorrect.

Could you please take a look at the F2802xAdcTempSensor example?

Gregory Helton said:
I am still unclear as to whether or not I need to trigger both SOCA and SOCB for round-robbin SOC setups on ADC conversions that span channels across ADCINAx and ADCINBx. Do I need to set the SOC trigger for ADCSOCA on SOC setups that are to convert channels located on ADCINA, and ADCSOCB on SOC setups that are to convert channels on ADCINB ?

The PWM module can generate SOCA and SOCB events. These are different from the 16 ADC SOCs.

Each ADC SOC can be triggered by many different sources, including SOCA or SOCB.

Each ADC SOC can be assigned to any ADC channel.

Best Regards,

Ben Collier

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TMS320F28035-EP: EPWM4 CMPA trigger multiple ADC conversions