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Tool/software:
Hi champs,
I am asking this for our customer.
Is it possible to dynamically change flash allocation to CPU1/CPU2?
This can be useful for firmware update using only one kernel by CPU for programming all 5 flash banks.
For example,
Case 1:
// Normal state
Bank0/1/2 -> CPU1
Bank3/4 -> CPU2.
// Firmware update state
Stop all application
CPU1 holds CPU2 in reset
CPU1 maps all 5 flash banks only to CPU1
CPU1 to erase and program all banks in combined binary or hex image.
CPU1 to software reset to normal state
Case 2:
Flash bank 4 accessed by CPU1 and CPU2 alternatively.
The user is responsible that CPU1 and CPU2 cannot access bank4 at the same time.
It's like a certain GPIOx is accessed by either CPU1 or CPU2 at a time.
Are the above cases viable?
Hi Wayne,
The expert is currently out of office, so please expect a delay in response. Thank you.
Best Regards,
Aishwarya
Hello Wayne,
Sorry for the late response on this one. The Flash bank does not need to be "assigned" to CPU1 for CPU1 to perform program and erase operations. CPU1 can program and erase all banks when it has control of the Flash wrapper by writing to the FLASHCTLSEM IPC register. CPU1 can grab the semaphore, do whatever programming and erasing needs to be done, and then release it.
For more info, please refer to section 12.6.1 (Flash Controller Access Semaphore) in the TRM.
Best regards,
Ibukun