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Tool/software:
This is about the amplitude of the crystal oscillator input to the microcontroller.
I understand that it is better to have a low amplitude for the input signal, but I would like to confirm the following additionally.
- Is there a possibility of misjudgment if the amplitude is so low that it falls below the microcontroller's threshold level?
- If the amplitude is not constant and fluctuates up and down due to some influence, will the internal clock period fluctuate, resulting in an error frame in CAN communication?
Hi Yasuhiro,
F28030 crystal circuit is 1.8V level. Ensure that the high level (VIH) and low level (VIL) drives is more than (0.8*1.80) 1.44v for VIH and less than (0.2*1.80) 0.36v for VIL. Outside of these levels, the clock input may interpret a missing clock and would force the MCD (missing clock detection circuit) to activate and initiate a clock recovery sequence and would default to lower internal clock to prevail to keep the microcontroller running to avoid system hang up. This will cause interruption to currently running process and any CAN communication as well. This is the potential effect of amplitude changes that do not meet the VIH/VIL criteria.
If there is interference in the clock where there may be glitches that would be interpreted as additional cycles and if this is persistent, the PLL may fail to lock and may initate a relocking sequence then would interrupt ongoing processes like CAN communication.
Regards,
Joseph