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UniFlash F28069 problem writing to flash

Other Parts Discussed in Thread: UNIFLASH, CONTROLSUITE

Hi,

I am trying to use Uniflash to write a bin file (created by hex2000) to flash. I have a 62kB bin file which I am attempting to write to address 0x3F0000. I should have 32Kw available. Here is the error I am running into:

[09:40:25] C28xx: Writing Flash @ Address 0x003F0000 of Length 0x00003FF8

[09:40:25] C28xx: Erasing Flash Sector A

[09:40:27] C28xx: Erasing Flash Sector B

[09:40:28] C28xx: Erasing Flash Sector C

[09:40:30] C28xx: Erasing Flash Sector D

[09:40:32] C28xx: Erasing Flash Sector E

[09:40:33] C28xx: Erasing Flash Sector F

[09:40:35] C28xx: Erasing Flash Sector G

[09:40:36] C28xx: Erasing Flash Sector H

[09:40:41] C28xx: Finish Writing Flash @ Address 0x003F0000 of Length 0x00003FF8

[09:40:44] C28xx: Writing Flash @ Address 0x003F7FF0 of Length 0x00003B00

[09:40:45] ERROR >> C28xx: Flash Programmer: Error encountered when writing to flash memory

[09:40:45] ERROR >> C28xx: Error Writing Flash @ Address 0x003F7FF0 of Length 0x00003B00


 I am not sure why it jumps to address 0x003F7FF0. Shouldn't each address location be 2 bytes?

  • Hi,

    I hope your cmd file is configured properly. Also can you please check memory allocation, for any overflows. 

    For F28069, I've attached the memory windows: (please cross check)

    Regards,

    Gautam

  •  The memory allocation is good. The .out file programs correctly. After messing around with it for a while, I was able to program the .bin file, but I had to break the file down to multiple smaller ones (<32 KB) and program one after the other choosing the memory locations. I programmed the first file at address (0x3F0100) and the other file was programmed at (0x3F0100 + file size of the first file). I would prefer to be able to program the .bin file all at once instead of breaking it down. Is there some setting I am overlooking? There does not seem to be much I could change in Uniflash.

  • Hi,

    I would prefer to be able to program the .bin file all at once instead of breaking it down.

    Very True, you should be able to.

    Is there some setting I am overlooking?

    There is no setting as such but there is some issue with the cmd file. Why don't you check default cmd files available in controlSuite??

    Regards,

    Gautam

  • I am using a cmd file that was provided (F28069.cmd) with some modifications. The .out file programs with no problems. Here is another example. I have a bigger .bin file that I program using a different tool other than Uniflash. The file is 128KB and I program it to address 0x3DC000. It writes to flash with no problems. When I use Uniflash however, I get this:

    [10:17:58] C28xx: Writing Flash @ Address 0x003DC000 of Length 0x00003FF8

    [10:17:59] C28xx: Erasing Flash Sector A

    [10:18:00] C28xx: Erasing Flash Sector B

    [10:18:01] C28xx: Erasing Flash Sector C

    [10:18:03] C28xx: Erasing Flash Sector D

    [10:18:04] C28xx: Erasing Flash Sector E

    [10:18:06] C28xx: Erasing Flash Sector F

    [10:18:07] C28xx: Erasing Flash Sector G

    [10:18:09] C28xx: Erasing Flash Sector H

    [10:18:15] C28xx: Finish Writing Flash @ Address 0x003DC000 of Length 0x00003FF8

    [10:18:19] C28xx: Writing Flash @ Address 0x003E3FF0 of Length 0x00003FF8

    [10:18:23] C28xx: Finish Writing Flash @ Address 0x003E3FF0 of Length 0x00003FF8

    [10:18:27] C28xx: Writing Flash @ Address 0x003EBFE0 of Length 0x00003FF8

    [10:18:32] C28xx: Finish Writing Flash @ Address 0x003EBFE0 of Length 0x00003FF8

    [10:18:36] C28xx: Writing Flash @ Address 0x003F3FD0 of Length 0x00003FF8

    [10:18:40] C28xx: Finish Writing Flash @ Address 0x003F3FD0 of Length 0x00003FF8

    [10:18:44] WARNING >> C28xx: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.

    [10:18:44] ERROR >> C28xx: File Loader: Data verification failed at address 0x003FBFC0 Please verify target memory and memory map.


    I checked the map file and everything looks ok. Here is my issue. If the file is 128KB and I am starting at address 0x3DC000, shouldn't the process stop at address 0x3EC000

  • Hi,

    I'll emphasize again on the same thing for:

    [10:18:44] WARNING >> C28xx: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.

    [10:18:44] ERROR >> C28xx: File Loader: Data verification failed at address 0x003FBFC0 Please verify target memory and memory map.

    Please check your linker .cmd file. The above is the case of memory conflict.

    Regards,

    Gautam

  • Hello,

    I am not sure if I am right.

    ismail ghazy said:
    If the file is 128KB and I am starting at address 0x3DC000, shouldn't the process stop at address 0x3EC000

    The maximum size of on-chip flash of F28069 is 128K (that written/read per word - 16 bits), so if your file is 128K, maybe you should write it from the beginning of the flash (it means from 0x3D8000) and the flash then will be full written until 0x3F7FF0 (I don't know how Uniflash writes/reads the memory but maybe it writes your 128KB file as 128K Words)

    In cmd file, usually it is written:

    FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
    CSM_RSVD : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
    BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */

    So if Uniflash writes your 128KB file as 128K Words, it can not be fully written for 128K.

    If you write the smaller size of the file, it will be written properly by Uniflash as long as the size is under 128K.

    Have you tried to write totally all of the files (that less than 32 KB as you said) to the flash?

    This is only my guest. Maybe this is not the problem anyway.

    Hope you can solve your problem soon.

    Best regards,

    Maria

  • Maria,

    maybe it writes your 128KB file as 128K Words

    That is what I think is happening when it is one long file. I have a feeling there is something wrong with the Uniflash flashing algorithm for the .bin file on this chip.

    Have you tried to write totally all of the files (that less than 32 KB as you said) to the flash

    Yes, and it works fine that way. When I break the file down to smaller ones and choose the addresses to be programmed.

    Thanks

  • Gautam,

    I attached the .cmd file I am using.

    8688.F28069 cmd.txt
    /*
    // TI File $Revision: /main/3 $
    // Checkin $Date: March 3, 2011   13:45:53 $
    //###########################################################################
    //
    // FILE:    F28069.cmd
    //
    // TITLE:   Linker Command File For F28069 Device
    //
    //###########################################################################
    // $TI Release: $ 
    // $Release Date: $ 
    //###########################################################################
    */
    
    /* ======================================================
    // For Code Composer Studio V2.2 and later
    // ---------------------------------------
    // In addition to this memory linker command file,
    // add the header linker command file directly to the project.
    // The header linker command file is required to link the
    // peripheral structures to the proper locations within
    // the memory map.
    //
    // The header linker files are found in <base>\F2806x_headers\cmd
    //
    // For BIOS applications add:      F2806x_Headers_BIOS.cmd
    // For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
    ========================================================= */
    
    /* ======================================================
    // For Code Composer Studio prior to V2.2
    // --------------------------------------
    // 1) Use one of the following -l statements to include the
    // header linker command file in the project. The header linker
    // file is required to link the peripheral structures to the proper
    // locations within the memory map                                    */
    
    /* Uncomment this line to include file only for non-BIOS applications */
    /* -l F2806x_Headers_nonBIOS.cmd */
    
    /* Uncomment this line to include file only for BIOS applications */
    /* -l F2806x_Headers_BIOS.cmd */
    
    /* 2) In your project add the path to <base>\F2806x_headers\cmd to the
       library search path under project->build options, linker tab,
       library search path (-i).
    /*========================================================= */
    
    /* Define the memory block start/length for the F2806x
       PAGE 0 will be used to organize program sections
       PAGE 1 will be used to organize data sections
    
       Notes:
             Memory blocks on F28069 are uniform (ie same
             physical memory) in both PAGE 0 and PAGE 1.
             That is the same memory region should not be
             defined for both PAGE 0 and PAGE 1.
             Doing so will result in corruption of program
             and/or data.
    
             Contiguous SARAM memory blocks can be combined
             if required to create a larger memory block.
    */
    
    #define FLASH_ENTRY_BASE        0x003F7FF6
    #define FLASH_ENTRY_LENGTH      0x00000002
    #define FLASH_RESET_BASE        0x003F7C00
    #define FLASH_RESET_LENGTH      0x00000100
    #define FLASH_BOOT_BASE         0x003F0120
    #define FLASH_BOOT_LENGTH       0x00007AE0
    #define BOOT_HEADER_BASE        0x003F0100
    #define BOOT_HEADER_LENGTH      0x00000020
    #define ROMVECTS_BOOT_BASE      0x003F0000
    #define ROMVECTS_BOOT_LENGTH    0x00000100
    #define FLASH_PARAM_BASE        0x003EC000
    #define FLASH_PARAM_LENGTH      0x00004000
    #define FLASH_MAIN_BASE         0x003DC140
    #define FLASH_MAIN_LENGTH       0x0000FEC0
    #define MAIN_LINK_TABLE_BASE    0x003DC13A
    #define MAIN_LINK_TABLE_LENGTH  0x00000006
    #define ROMVECTS_MAIN_BASE      0x003DC03A
    #define ROMVECTS_MAIN_LENGTH    0x00000100
    #define FLASH_HEADER_BASE       0x003DC000
    #define FLASH_HEADER_LENGTH     0x0000003A
    #define FLASH_ELOG_BASE         0x003D8000
    #define FLASH_ELOG_LENGTH       0x00004000
    
    MEMORY
    {
    PAGE 0 :   /* Program Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
       FLASH            : origin = FLASH_MAIN_BASE, length = FLASH_MAIN_LENGTH
       ROMVECTS         : origin = ROMVECTS_MAIN_BASE, length = ROMVECTS_MAIN_LENGTH
       FLASH_PARAM      : origin = FLASH_PARAM_BASE, length = FLASH_PARAM_LENGTH
       FLASH_RESET      : origin = FLASH_RESET_BASE, length = FLASH_RESET_LENGTH
       FLASH_HEADER     : origin = FLASH_HEADER_BASE, length = FLASH_HEADER_LENGTH
       MAIN_LINK_TABLE  : origin = MAIN_LINK_TABLE_BASE, length = MAIN_LINK_TABLE_LENGTH
       BOOT_HEADER      : origin = BOOT_HEADER_BASE, length = BOOT_HEADER_LENGTH
       FLASH_ENTRY      : origin = FLASH_ENTRY_BASE, length = FLASH_ENTRY_LENGTH
    
       OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
       RAM_PARAM        : origin = 0x8300, length = 0xC00
    
    //   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
    //   FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
    //   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
    //   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */
    //   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
    //   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
    //   FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
       CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
    //   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
       CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
    
       FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	  /* FPU Tables in Boot ROM */
       IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
       IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
       IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */
    
       ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
       RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
       VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
    
    PAGE 1 :   /* Data Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
               /* Registers remain on PAGE1                                                  */
    
       BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
    //   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
    //   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
       PIEVECT     : origin = 0x00000D00, length = 0x00000100
       M0_M1       : origin = 0x000050, length = 0x0007B0     /* on-chip RAM block M0 & M1 */
       SHARED_RAM  : origin = 0x008000, length = 0x000100
       LINKED_RAM  : origin = 0x008100, length = 0x000100
       SCRATCH_RAM : origin = 0x008200, length = 0x000100
    //   RAML2       : origin = 0x008C00, length = 0x000400     /* on-chip RAM block L2 */
    //   RAML3       : origin = 0x009000, length = 0x001000	  /* on-chip RAM block L3 */
    //   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
       RAM_LX      : origin = 0x008F00, length = 0x00B100
    //   RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
    //   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
    //   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
    //   RAML8       : origin = 0x012000, length = 0x002000     /* on-chip RAM block L8 */
       USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */   
    //   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */
    }
    
    /* Allocate sections to memory blocks.
       Note:
             codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                       execution when booting to flash
             ramfuncs  user defined section to store functions that will be copied from Flash into RAM
    */
    
    
    SECTIONS
    {
    
       /* Allocate program areas: */
       .cinit              : > FLASH,     PAGE = 0
       .pinit              : > FLASH,     PAGE = 0
       .text               : > FLASH,      PAGE = 0
       codestart           : > FLASH_ENTRY,      PAGE = 0
       ramfuncs            : LOAD = FLASH,
                             RUN = RAM_PARAM,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             PAGE = 0
    
       csmpasswds          : > CSM_PWL_P0, PAGE = 0
       csm_rsvd            : > CSM_RSVD,   PAGE = 0
    
       /* Allocate uninitalized data sections: */
       .cio                : > RAM_LX,      PAGE = 1
       .stack              : > M0_M1,      PAGE = 1
       .ebss               : > RAM_LX,  PAGE = 1
       .esysmem            : > RAM_LX,      PAGE = 1
       .scratchRam         : > SCRATCH_RAM,  PAGE = 1
       .linkedRam          : > LINKED_RAM,  PAGE = 1
       .sharedRam          : > SHARED_RAM,  PAGE = 1
    
       /* Initalized sections to go in Flash */
       /* For SDFlash to program these, they must be allocated to page 0 */
       .switch             : > FLASH,     PAGE = 0
       .paramSectorDefs    : > FLASH_PARAM,     PAGE = 0
    //   .paramSectorDefsInFlash  : > FLASH_PARAM,     PAGE = 0
       .resetSectorDefs    : > FLASH_RESET,     PAGE = 0
       .mainFlashHeader     : > FLASH_HEADER  PAGE = 0
       .bootFlashHeader		: > BOOT_HEADER		PAGE = 0
    
       .econst:_ti_sysbios_family_c28_Hwi_vectors : > ROMVECTS, PAGE = 0,
                              LOAD_START(_hwi_vec_loadstart),
                              LOAD_END(_hwi_vec_loadend),
    //                          SIZE(_hwi_vec_loadsize),
                              RUN_START(_hwi_vec_runstart)
    
        .econst             : > FLASH,     PAGE = 0
    
       /* Allocate IQ math areas: */
    //   IQmath              : > FLASH,     PAGE = 0            /* Math Code */
    //   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
       
       /* Allocate FPU math areas: */
       FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
       
    //   DMARAML5	           : > RAML5,      PAGE = 1
    //   DMARAML6	           : > RAML6,      PAGE = 1
    //   DMARAML7	           : > RAML7,      PAGE = 1
    //   DMARAML8	           : > RAML8,      PAGE = 1
    
      /* Uncomment the section below if calling the IQNexp() or IQexp()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
    
       }
       */
        /* Uncomment the section below if calling the IQNasin() or IQasin()
           functions from the IQMath.lib library in order to utilize the
           relevant IQ Math table in Boot ROM (This saves space and Boot ROM
           is 1 wait-state). If this section is not uncommented, IQmathTables2
           will be loaded into other memory (SARAM, Flash, etc.) and will take
           up space, but 0 wait-state is possible.
        */
        /*
        IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
        {
    
                   IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
    
        }
        */
    
       /* .reset is a standard section used by the compiler.  It contains the */
       /* the address of the start of _c_int00 for C Code.   /*
       /* When using the boot ROM this section and the CPU vector */
       /* table is not needed.  Thus the default type is set here to  */
       /* DSECT  */
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT
       vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT
    
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    
    

  • Hi,

    Try using this .cmd file:

    0743.F28069.cmd.txt
    /*
    //###########################################################################
    //
    // FILE:    F28069.cmd
    //
    // TITLE:   Linker Command File For F28069 Device
    //
    //###########################################################################
    // $TI Release: F2806x C/C++ Header Files and Peripheral Examples V136 $ 
    // $Release Date: Apr 15, 2013 $ 
    //###########################################################################
    */
    
    /* ======================================================
    // For Code Composer Studio V2.2 and later
    // ---------------------------------------
    // In addition to this memory linker command file,
    // add the header linker command file directly to the project.
    // The header linker command file is required to link the
    // peripheral structures to the proper locations within
    // the memory map.
    //
    // The header linker files are found in <base>\F2806x_headers\cmd
    //
    // For BIOS applications add:      F2806x_Headers_BIOS.cmd
    // For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
    ========================================================= */
    
    /* ======================================================
    // For Code Composer Studio prior to V2.2
    // --------------------------------------
    // 1) Use one of the following -l statements to include the
    // header linker command file in the project. The header linker
    // file is required to link the peripheral structures to the proper
    // locations within the memory map                                    */
    
    /* Uncomment this line to include file only for non-BIOS applications */
    /* -l F2806x_Headers_nonBIOS.cmd */
    
    /* Uncomment this line to include file only for BIOS applications */
    /* -l F2806x_Headers_BIOS.cmd */
    
    /* 2) In your project add the path to <base>\F2806x_headers\cmd to the
       library search path under project->build options, linker tab,
       library search path (-i).
    /*========================================================= */
    
    /* Define the memory block start/length for the F2806x
       PAGE 0 will be used to organize program sections
       PAGE 1 will be used to organize data sections
    
       Notes:
             Memory blocks on F28069 are uniform (ie same
             physical memory) in both PAGE 0 and PAGE 1.
             That is the same memory region should not be
             defined for both PAGE 0 and PAGE 1.
             Doing so will result in corruption of program
             and/or data.
    
             Contiguous SARAM memory blocks can be combined
             if required to create a larger memory block.
    */
    
    MEMORY
    {
    PAGE 0 :   /* Program Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
       RAML0       : origin = 0x008000, length = 0x000800     /* on-chip RAM block L0 */
       RAML1       : origin = 0x008800, length = 0x000400     /* on-chip RAM block L1 */
       OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
    
       FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
       FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
       FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
       FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */   
       FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
       FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
       FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
       CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
       BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
       CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
    
       FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	  /* FPU Tables in Boot ROM */
       IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
       IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
       IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */
    
       ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
       RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
       VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
    
    PAGE 1 :   /* Data Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
               /* Registers remain on PAGE1                                                  */
    
       BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
       RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
       RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
       RAML2       : origin = 0x008C00, length = 0x000400     /* on-chip RAM block L2 */
       RAML3       : origin = 0x009000, length = 0x001000	  /* on-chip RAM block L3 */
       RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
       RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
       RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
       RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
       RAML8       : origin = 0x012000, length = 0x002000     /* on-chip RAM block L8 */
       USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */   
       FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */     
    }
    
    /* Allocate sections to memory blocks.
       Note:
             codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                       execution when booting to flash
             ramfuncs  user defined section to store functions that will be copied from Flash into RAM
    */
    
    
    SECTIONS
    {
    
       /* Allocate program areas: */
       .cinit              : > FLASHA,     PAGE = 0
       .pinit              : > FLASHA,     PAGE = 0
       .text               : > FLASHA,     PAGE = 0
       codestart           : > BEGIN,      PAGE = 0
       ramfuncs            : LOAD = FLASHD,
                             RUN = RAML0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
    						 LOAD_SIZE(_RamfuncsLoadSize),
                             PAGE = 0
    
       csmpasswds          : > CSM_PWL_P0, PAGE = 0
       csm_rsvd            : > CSM_RSVD,   PAGE = 0
    
       /* Allocate uninitalized data sections: */
       .stack              : > RAMM0,      PAGE = 1
       .ebss               : > RAML2,      PAGE = 1
       .esysmem            : > RAML2,      PAGE = 1
    
       /* Initalized sections to go in Flash */
       /* For SDFlash to program these, they must be allocated to page 0 */
       .econst             : > FLASHA,     PAGE = 0
       .switch             : > FLASHA,     PAGE = 0
    
       /* Allocate IQ math areas: */
       IQmath              : > FLASHA,     PAGE = 0            /* Math Code */
       IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
       
       /* Allocate FPU math areas: */
       FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
       
       DMARAML5	           : > RAML5,      PAGE = 1
       DMARAML6	           : > RAML6,      PAGE = 1
       DMARAML7	           : > RAML7,      PAGE = 1
       DMARAML8	           : > RAML8,      PAGE = 1   
    
      /* Uncomment the section below if calling the IQNexp() or IQexp()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
    
       }
       */
        /* Uncomment the section below if calling the IQNasin() or IQasin()
           functions from the IQMath.lib library in order to utilize the
           relevant IQ Math table in Boot ROM (This saves space and Boot ROM
           is 1 wait-state). If this section is not uncommented, IQmathTables2
           will be loaded into other memory (SARAM, Flash, etc.) and will take
           up space, but 0 wait-state is possible.
        */
        /*
        IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
        {
    
                   IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
    
        }
        */
    
       /* .reset is a standard section used by the compiler.  It contains the */
       /* the address of the start of _c_int00 for C Code.   /*
       /* When using the boot ROM this section and the CPU vector */
       /* table is not needed.  Thus the default type is set here to  */
       /* DSECT  */
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT
       vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT
    
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    
    

    Regards,

    Gautam

  • Didn't work. It is still having the same issue.

  • Hi Ismail!

    Try to go through this thread http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/299958/1045384.aspx#1045384. Perhaps you will find something helpful.

    Regards,

    Igor

  • Thank you Igor. Good links. However; I am not having an issue with hex2000 utility or post builds. I believe the issue is with the Uniflash software.

  • Are there any other suggestions?

  • Hi Ismail,

    I think I know whats going on here.  You're right to question the linker file first as this is what allocates the code and data in memory, but there are other things at play here...namely hex2000.  I believe the out file the compiler/linker is generating is correct, but when hex2000 converts this into the bin format it is messing with the addressing.

    One of the parameters hex2000 can optionally take is called romwidth.  This helps tell hex2000 how the target memory is organized.  This feature is mainly used on devices that have an external memory with a width different from that of the MCU.  By default if you don't supply this parameter it builds files with the wrong formatting to be stored in the MCU's flash.

    My recommendation would be to switch to a more human readable format like Hex or Srec and generate these files with differing romwidth parameters (8, 16, and 32).  You can then compare this to the device's memory after letting CCS program the outfile.  Whichever file matches the device's memory was generated with the correct romwidth parameter.  I would tell you what that value is, but honestly its been a while since I played with this and I don't remember.

    Once you know the right romwidth parameter, generate a bin file with this in the arguments and then try programming with uniflash.

    BR,

  •  Thank you for your quick response Trey. If I understand your post correctly, I had already tried changing the romwidth parameter. I also ran across this post http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/228101.aspx . Which I think addresses the issue you are pointing out.

    Here is whats confusing me. If I try to program a file that is 128KB and I am starting at address 0x3DC000, shouldn't the process stop at address 0x3EC000? Since each address location is 16bits

    Thanks

  • Ismail,

    No problem, happy to help out.

    Hrmm, yes I believe it should end around that address.  Have you tried other formats besides bin in uniflash?  Maybe TI-TXT or just the out file?  I specifically like hex and TI-TXT files as they are easily readable whereas a binary is hard to decipher.

    In the mean time, I'm emailing our contact on the Uniflash team to see if he has any ideas.

    BR,

  • Ismail,

    Could you please send me your .out file, the .bin file, the command you used to generate the .bin file from hex util, and your linker cmd file to v-yang@ti.com ? I will try to recreate the problem and debug.

    Thanks,

    Victor

  • yes I can program the .out file using uniflash. I can also program the .bin file but I have to break the .bin file to smaller sized ones and program one after the other.

  • Vector,

    I will do that first thing tomorrow morning.

    Thank you

  • Hi All,

    This is a bug with the loader. It affects binary file loads on targets with addressable unit size larger than 1 byte and file load size larger the 0x3FF0. This will be fixed in beta 3 of ccs 6.0 coming out sometime in Q1. It's being tracked by cq SDSCM00049204.

    Meantime a work around to this is to call the gel function DEBUG_SetBinFileLoadBlockSize(0xF600) to set the block size equal to the file.

    Regards,

    Mandeep

     

  • Thank you for the response Mandeep. This solution worked in that it programmed the whole file without skipping sections of memory and without throwing errors. However; it is programming the file byte swapped and I wasn't sure if there was some setting I could change or line of code I code add to the script.

    Thank you