• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 82 subscribers
  • Views 1225 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Multiple byte transfer using SCI FIFO : First byte missed

Varun Kumar3
Intellectual 285 points
Other Parts Discussed in Thread: CONTROLSUITE

Hello,

I am using SCI FIFO (4 level) to transfer chunk of data (currently in loopback mode to test the driver). 

Issue:

1. I find first byte is always missed which is send from TX INTR. (If I send first byte as dummy data and then load FIFO with correct 4 bytes, then all is received correctly.)

This is not mentioned in FIFO operation section of controller manual literature. 

Whereas in document SCI-A_Tech Ref Manual I find section 1.1.5.3 (Wake-Up Temporary Flag) which talks about first byte being ignored in case of block transfer.

Conclusion: So, all the time I need to send 5 Bytes instead of 4 bytes in case of FIFO operation to work properly.

Can someone confirm my understanding? 

  • 0
    Guru 192875 points

    Hi,

    The above scenario that you've described should not happen. Did you refer to the SCI FIFO configuration/ initialization of the example project in controlSuite ie scia_loopback? This code works like a charm and has no issues.

    Regards,

    Gautam

  • 0 in reply to Gautam Iyer
    Intellectual 285 points

    Hi Gautam,

    thanks for quick reply. below are configuration values. Which seems to be OK as per manual:

    SciaRegs.SCICCR.all = 0x0007;
    SciaRegs.SCICCR.bit.LOOPBKENA = 1;

    SciaRegs.SCICTL2.bit.TXINTENA = 1;

    SciaRegs.SCICTL2.bit.RXBKINTENA = 1;


    SciaRegs.SCIHBAUD = 0x0000;
    SciaRegs.SCILBAUD = SCI_PRD;

    SciaRegs.SCIFFTX.all = 0xE020;// E090 //0xC022; think to clr bit 6 also later

    SciaRegs.SCIFFRX.all = 0x2034; //0x2034; //0x0022;
    SciaRegs.SCIFFCT.all = 0x00;

    SciaRegs.SCICTL1.all = 0x0023;

  • 0 in reply to Varun Kumar3
    Guru 192875 points

    Does the sample code "Example_2806xScia_FFDLB.c" work for you or it too behaves the same way?

  • 0 in reply to Gautam Iyer
    Intellectual 285 points

    Gautam,

    This example has worked well for me in past, and I have retained most of its configuration other than FIFO water levels and interrupt settings.

    this example is not interrupt based. I receive RX interrupt after 4 bytes are received in FIFO buffer. Somehow, the first byte is not getting pushed into FIFO and getting discarded.

    ==> In my first post, I have mentioned about reference manual section where this behavior is OK during multiprocessor communication mode. 

    I wanted to know, if it is OK for normal multibyte transfer mode also OR I am missing some settings.. (I have pushed all settings in previous post which are used by me)

  • 0 in reply to Varun Kumar3
    Intellectual 285 points

    Guys, 

    it worked now. Issue was with SCI configuration register settings for FFTX and FFRX. 

  • 0 in reply to Varun Kumar3
    Guru 192875 points

    That's Great, Varun.

    Good Luck & Regards,

    Gautam