The TMS320F2837xD Technical Manual Revision E has updates to the DMA section 4:
Section 4.5.2 Channel 1 High Priory Mode now contains the note:
NOTE: High-priority mode and one shot mode may not be used at the same time.
Section 4.6 Address Pointer and Transfer Control also has a similar note added for One Shot Mode.
- Why have these notes been added?
- What happens when High-priority mode and one shot mode are both used at the same time?
- Do other members of the C2000 also have a similar issue? (There are no similar notes for the TMS320F2833x or TMS320F2806x.)
- Why is this issue not included in the Silicon Errata for the TMS320F2837xD?
Application Information
We use both high-priority mode and one-shot mode in our firmware for the TMS320F28377D. This has been operational for >12 months and we have not noticed any problems associated with the DMA. Similar code has been operating on the TMS320F28335 and TMS320F28062 for years without incident.
In our application we use software initiated DMA transfers of relatively large blocks and hardware initiated transfers of smaller blocks. Software initiated DMA transfers and some hardware initiated transfers have a single trigger for each transfer. To share DMA bandwidth we prefer to use one-shot mode with a small burst-size. Then transfers can occur concurrently for several DMA channels (each burst by burst). Figure 4.7 certainly implies that this is possible. (The yes branch from ONE-SHOT == 1? is labelled as a point where state machine branches to next channel are possible.) The hardware initiated DMA with the lowest latency requirement is set for CH1 and the high-priority mode is enabled. The scheme would probably work OK without the high-priority mode enabled, but the timing analysis would be more difficult. We will only disable the high-priority mode if absolutely necessary.