F28069F SPI Master slave communication between two microcontroller

Hello Team.

This discussion is continuation of my previous thread since I didn't get any response/suggestions on that thread further, so I have created new thread. 

previous discussion link > e2e.ti.com/.../1889748

I have established SPI communication between both the boards.

But now the problem, data I receive in slave from the master is getting shifted.

An example of the data being transmitting from Master to Slave.
Master || Slave 

0x1111 || 0x4444 
0x2222 || 0x8888
0x0010 || 0x0040
0xF00F || 0xC03F.

In the above example, data is getting shifted by one bit.
At times, bits gets shifted by two or three bits place. Same happens when the data is transmitted from slave to master too.

When the data is transmitted from master to slave, data is written to  SPITXBUF register in the master, received data  is read from the SPIRXBUF register  of the slave.

Settings in my Master and slave programs are as follows : 

SysCtrlRegs.LOSPCP.all = 0x0006; / same clk for both master and slave.

SPI intialization for master as follows :

SpibRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI
SpibRegs.SPICCR.all=0x000F; //16-bit character, Loopback mode
SpibRegs.SPICTL.all=0x0017; //Interrupt enabled, Master/Slave XMIT enabled
SpibRegs.SPISTS.all=0x0000;
SpibRegs.SPIBRR=0x007F; // Baud rate
SpibRegs.SPIFFTX.all=0xC022; // Enable FIFO's, set TX FIFO level to 4
SpibRegs.SPIFFRX.all=0x0022; // Set RX FIFO level to 4
SpibRegs.SPIFFCT.all=0x00;
SpibRegs.SPIPRI.all=0x0010;
SpibRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI
SpibRegs.SPIFFTX.bit.TXFIFO=1;
SpibRegs.SPIFFRX.bit.RXFIFORESET=1;

SPI intialization for Slave as follows :
SpibRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI
SpibRegs.SPICCR.all=0x000F; //16-bit character, Loopback mode
SpibRegs.SPICTL.all=0x0013; //Interrupt enabled, Master/Slave XMIT enabled
SpibRegs.SPISTS.all=0x0000;
SpibRegs.SPIBRR=0x007F; // Baud rate
SpibRegs.SPIFFTX.all=0xC022; // Enable FIFO's, set TX FIFO level to 4
SpibRegs.SPIFFRX.all=0x0022; // Set RX FIFO level to 4
SpibRegs.SPIFFCT.all=0x00;
SpibRegs.SPIPRI.all=0x0010;
SpibRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI
SpibRegs.SPIFFTX.bit.TXFIFO=1;
SpibRegs.SPIFFRX.bit.RXFIFORESET=1;

Please let me know if anything has to be checked or changed.

Please find the attached screenshot.

In the above screen:

Yellow waveform : MOSI.

Green waveform : SYSCLK  on the master side.

Pink waveform : SPISTE pin output, which is connected to ground.

Blue waveform : SYSCLK on the  slave side. 

Thanks in advance.

Best regards,
Chetan.