F28379D Delfino Experimenter Kit

Hi Dany,

Using an external voltage reference will definitely result in an ADC system with better performance.  This is how we internally test the ADC and is how we get the values we have put in the datasheet.

Connecting the reference pins up to 3.3V/VDDA will result in a valid ADC, however there will likely be more noise.  The exact amount of noise will be dependent on the schematic, layout, etc of the system the F28379D is being used in.  When VDDA drives VREFHI, any change in VDDA (over temperature, any change in voltage due to load regulation of the source, etc) will result in error in the sampled result.  If VDDA/VSSA are carefully handled, it is theoretically possible that noise could be made relatively small. 

You are correct to say that using a 3.0V reference will result in the full-scale range being reduced.  However within the valid range, the analog system will have better ENOB.  It's also worth noting that in many circumstances, the board designer will have flexibility in choosing what voltage goes into the ADC.  For example, the resistor values in a voltage divider or the opamp gain/shunt value is flexible in a doing shunt measurement.

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I'm assuming the VREF/2 adjustment idea is in reference to when you tie the reference input to VDDA.  If I understand, your plan assumes that noise is consistent at different locations on the board - which isn't necessarily true.  Also note that to measure VREFHI/2 with an ADC, that ADC will be referencing VREFHI itself to convert the voltage sampled by the ADC.

Ideas for calibration are valid though.  For example, periodically sampling VREFLO can enable you to re-calibrate the ADC offset during runtime.  The datasheet offers more on this.


Thank you,
Brett

Hi Dany,

We don't have an official design which can be used.

The main task is in converting a +/- 12V input to a differential output whose range is matches the ADC.
(ie {-12V -> V+ = 0V, V- = 3.0V -> converts to value 0}, {+12V -> V+ = 3.0V, V- = 0V -> converts to value 65536}, and {0V -> V+ = 1.5V, V- = 1.5V -> converts to value 32768})

Several approaches may be feasible, but for each it would be a good idea to simulate whatever circuitry you plan on using beforehand to ensure validity.

1) Use single-ended opamps to generate a differential output.  This opamp circuity would contain elements to deamplify the input.  The following TIDesign may be helpful:
http://www.ti.com/lit/tidu038

2) Use a differential opamp to do something similar.  The following E2E post may be helpful:
https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/534361/1952725

For 1) and 2) some care may need to be taken to make sure that power is not applied to any ADC input prior to the device being powered.

3) Scale the input before-hand via something like resistive dividers and then have it go to the opamp circuitry.  You can then power the opamps with the signal that goes to the chip's VDDA.  This will help with power sequencing.

If you need more specific advice, it might be worthwhile to ask the amplifier portion of the e2e forum. 

Hopefully this helps!


Thank you,
Brett

Hi Brett,

As I mentionned earlier, I will have to convert not a +/-12V but a +/-10V input to the 12bit ADC (sampling rate at 10kHz). The current transducer manufacturer has some recommendations on how to design the ADC front end. I simulated a circuit with Tina V9.3 and I have a few questions:

*You will find attached my Tina project and the recommended analog front end desing.

1- Is it possible to add a common mode choke in the design.

2- I try to simulate a voltage divider with splitted up input resistors between the clamping diodes. If I used splited resistors in my design the voltage gain is not set proporley. Do you know why.

3- I used the OPA376 op amp for my design, is it a good choice for that kind of application.

4- I used one amplifier for gain divider and one amplifier for voltage filtering. Is it a good design practice or it would be a better choice to combine both stages. If using two stages is a good design practice, do the resistors of the low-pass filter should be higher than the actual values (I used Filter Pro to design the filter, Fc = 3kHz, 2 poles, Bessel, Sallen-Key) to match the previous stage.

5- Should I select a lower capacitor value for the passive RC filter.

ADC_Front_End.TSC

Best Regards

Hi Dany,

This is getting deeper into the signal chain and while we may be able to provide answers to your questions, you will likely get superior answers if you post these new questions on the TI E2E Precision Amplifiers forum:
https://e2e.ti.com/support/amplifiers/precision_amplifiers/

They will likely be able to help you best with the opamp selection and what the best circuit topology is.  Feel free to reference this post in your post there. 

Furthermore, feel free to return to the C2000 forum if you'd like more help on the interface to the ADC (perhaps to help ensure good ADC settling with our ADC and the selected circuit). 
[Note that a model of this device's internal ADC sampling circuit can be found in the device datasheet]

Hopefully this helps!


Thank you,
Brett