LAUNCHXL-F28377S Glitch on GPIO63 configured as SPISIMOB

Bob,

Can you elaborate a bit more here? I am not sure what the problem is other than you saying that there is a glitch that goes away when you ground U2.

- What are you trying to accomplish?
- Is there application code running during a glitch?
- What affect does this glitch have on your system?

If you can share a bit more information, we might be able to assist better.

Thanks,
Mark

Hi Mark,
I am essentially running the Buck_VMC_F2837xS code with some added I/O
I have a mode that bypasses the Vout A/D and uses the SPI A master mode on TI uC. It works well.
SPISIMOA looks OK.
The master clocks out test data to a slave device.

I wanted to expand the capability for SPI B. I see glitches on SPISIMOB that sometimes line up with
SPICLKB and cause the slave to clock in corrupt values.
The glitch maybe data dependent. I think I saw it at a fixed value of
SpiaRegs.SPITXBUF=Vout1R; // xxx
SpibRegs.SPITXBUF=0x55aa; // xxx


// below are the GPIO settings

/* Disable internal pull-up for the selected output pins
for reduced power consumption */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.

GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO18 (EPWM10A)

/* Configure EPWM-10 pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be EPWM10 functional pins.
// Comment out other unwanted lines.

GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // 5=EPWM10A. Configure GPIO18 as EPWM10A
GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 1; // Configure GPIO18 as EPWM10A
//--------------------------------------------------------------------------------------
// GPIO-13 - PIN FUNCTION = LED D10 on the F2837xS LaunchPad
//--------------------------------------------------------------------------------------
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0; // 0=GPIO, 1=Resv, 2=Resv, 3=Resv
GpioCtrlRegs.GPADIR.bit.GPIO13 = 1; // 1=OUTput, 0=INput
GpioDataRegs.GPASET.bit.GPIO13 = 1; // Set High initially
//--------------------------------------------------------------------------------------
/// GPIO-11 - PIN FUNCTION = GPIO11 I_ISR_TOGGLE
//--------------------------------------------------------------------------------------
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // 0=GPIO, 1=Resv, 2=Resv, 3=Resv
GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // 1=OUTput, 0=INput
GpioDataRegs.GPASET.bit.GPIO11 = 0; // Set High initially

//--------------------------------------------------------------------------------------/
// SPIA
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA)
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA)
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA)
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA)

/* Set qualification for selected pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.

//xxx GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
//xxx GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
//xxx GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
//xxx GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)

/* Configure SPI-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be SPI functional pins.
// Comment out other unwanted lines.

GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0; // Re Configure GPIO18 as SPICLKA
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA

CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
//--------------------------------------------------------------------------------------/

// SPIB
//xxx GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up on GPIO63 (SPISIMOB)
//xxx GpioCtrlRegs.GPCPUD.bit.GPIO64 = 0; // Enable pull-up on GPIO64 (SPISOMIB)
//xxx GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (SPICLKB)
//xxx GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (SPISTEB)

/* Set qualification for selected pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.

//xxx GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // Asynch input GPIO63 (SPISIMOB)
//xxx GpioCtrlRegs.GPCQSEL1.bit.GPIO64 = 3; // Asynch input GPIO64 (SPISOMIB)
//xxx GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58 (SPICLKB)
//xxx GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (SPISTEB)

/* Configure SPI-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be SPI functional pins.
// Comment out other unwanted lines.
//xxx GPIO_setPinMuxConfig();
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // Configure GPIO63 as SPISIMOB
GpioCtrlRegs.GPBGMUX2.bit.GPIO63 = 3; // Configure GPIO63 as SPISIMOB
GpioCtrlRegs.GPCGMUX1.bit.GPIO64 = 3; // Re Configure GPIO64 as SPISOMIB
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 2; // Configure GPIO58 as SPICLKB
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 2; // Configure GPIO59 as SPISTEB
GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 1; // Configure GPIO58 as SPICLKB
GpioCtrlRegs.GPBGMUX2.bit.GPIO59 = 1; // Configure GPIO59 as SPISTEB
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // Configure GPIO64 as SPISOMIB

CpuSysRegs.PCLKCR8.bit.SPI_B = 1;

//--------------------------------------------------------------------------------------/

// GPIO-69 - PIN FUNCTION = GPIO69 XCLKOUT on the F2837xS LaunchPad
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 0; // 0 = GPIO69
GpioCtrlRegs.GPCDIR.bit.GPIO69 = 0; // 1=OUTput, 0=INput


// GPIO-73 - PIN FUNCTION = GPIO73 XCLKOUT on the F2837xS LaunchPad
//--------------------------------------------------------------------------------------
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XCLKOUT
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
// GPIO-84, GPIO-85 - PIN FUNCTION = SCITX and SCIRX
//--------------------------------------------------------------------------------------
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 1; // 5=SCITX
GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 1; // 5=SCITX
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 1; // 5=SCIRX
GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 1; // 5=SCIRX

- Do you have any oscilloscope captures of these glitches?
- Does the glitch coincide with any other events in the system? Does it always occur at the same time or is it randomly occurring?
- Is there anything connected to the QEP_B.2 Header? This is the other side of the level-shifter that you are disabling the output of. If you don't intend on connecting anything to the QEP_n headers, then I don't see a problem with grounding the OE pin. This will tristate the I/Os on U2, preventing any unwanted transitions.


On an unrelated note, please be sure that you configure the GPyGMUXn registers before configuring the GPyMUXn registers. There is a possibility of glitching on the IO during configuration if this is not done.

I have an old scope. The floppy disk is broken so I cannot store images.

It looked like the glitches were often a fixed period apart.

I don't have anything on the QEP_n headers.

Thanks for the GPyGMUXn tip.