TMS320C28346: /SPISTE Signal Stays Low & SPI Clk Never Stops

I programmed a C28346 Delfino microcontroller with a Simulink model someone else developed. I have the SPID port configured as a master and setup to send 16-bit data. I am getting SPI data out and the SPI Clock output is always running. The SPI Slave Select line stays low as well. This signal should return high and the SPI Clock output should stop after 16-bits have been transferred.

The Simulink model has the following code to initialize the SPI port.

//init_SPID_GPIO

GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (SPISIMOD)

GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // Configure GPIO48 as SPISIMOD

GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (SPISOMID)

GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // Configure GPIO49 as SPISOMID

GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (SPICLKD)

GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // Configure GPIO50 as SPICLKD

GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (SPISTED)

GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // Configure GPIO51 as SPISTED

// init spi D (current to super)

SpidRegs.SPICCR.bit.SPISWRESET = 0;

SpidRegs.SPICCR.bit.SPICHAR = 16-1; //16 databits; formula=DataBits-1; // Character length control

SpidRegs.SPICCR.bit.SPILBK = 0; //disable loopback

SpidRegs.SPICCR.bit.CLKPOLARITY = 0;// 1:Data is output on falling edge and input on rising edge; 0:Data is output on rising edge and input on falling edge.

SpidRegs.SPICTL.bit.TALK = 1; // Master/Slave transmit enable, 1=enabled, 0=disabled

SpidRegs.SPICTL.bit.MASTER_SLAVE = 1; // 0=slave, 1=master

SpidRegs.SPICTL.bit.CLK_PHASE = 0;// Clock phase ; 0: Data is output on the rising/falling edge (no delay); 1: Data is output one half-cycle before the first rising/falling edge

SpidRegs.SPIPRI.bit.FREE = 1; //Free run enabled, continue SPI operation regardless of suspend

SpidRegs.SPIBRR = 127; // Baud rate factor (for master only)

SpidRegs.SPIFFTX.bit.SPIFFENA = 1; // enable FIFO (both tx and rx)

SpidRegs.SPIFFRX.bit.RXFFIENA = 1; // enable rx fifo interrupts

SpidRegs.SPIFFTX.bit.TXFFIENA = 1; // enable tx fifo interrupts

SpidRegs.SPIFFRX.bit.RXFFIL = 14;//1; // Rx FIFO Interrupt Level

SpidRegs.SPIFFTX.bit.TXFFIL = 2; // Tx FIFO Interrupt Level

SpidRegs.SPIFFCT.all = 0;// no FIFO transmit delay

SpidRegs.SPICCR.bit.SPISWRESET = 1; // Enable SPI