Tool/software: Code Composer Studio
Hi,
I'm using TMS320F28035 (Piccolo) with CCS Vers. 6.1.0.00104 (and C code both for CPU and CLA) in order to control a boost converter in discontinuous conduction mode with Peak current mode controlPWM(choke current at the beginning of a switch interval should be zero and I'm testing this condition in CLA). CLA task1 executes the C code for controlling PWM1A in order to get constant output voltage from the converter.
If at the beginning of switch interval the current is greater than a threshold value I try to swith PWM1A off for the current switch interval (in the next interval it should turn on again automatically). Doing this via putting 0 into the DAC and with the help of the analog comparator works fine (but might be slower than necessary). I'd like better avoide the analog path and generate a SW trip to turn off PWM1A. Unfortunately this doesn't work and it seems to me that PWM1 simply stops (forever, which isn't what I intended, not at all). Could there be an adressing problem in the CLA (32 bit pointer in CPU, 16 bit pointer in CLA???) when I read and
write EPwm registers the same way in CPU and CLA?
Many thanks in advance for any helpful suggestions.
Regards,
Leo Rohrecker
// ===== initialization in CPU code: =====
EALLOW;
// Setup compare: A = PWM max DC, B = ADC SOC
EPwm1Regs.CMPA.half.CMPA = 0; // DC = 0
EPwm1Regs.CMPB = ADC_SOC_OFFSET;
// Clock ratios to SYSCLKOUT
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// period
EPwm1Regs.TBPRD = PWM_TIMER_TBPRD;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // max duty cycle
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // ADC SOC 1st group
// CBC trip, define an event (DCAEVT2)
// (see SPRUGE9E, Ex. 14)
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; // DCAH = comparator 1 output
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI; // DCAEVT2 = DCAH high (will become active as comp. output goes hi)
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // take async path
EPwm1Regs.TZSEL.bit.DCAEVT2 = 1; // enable CBC event
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWM1A will go low
EPwm1Regs.TZCTL.bit.TZB = TZ_NO_CHANGE; // EPWM1B unaltered
// define SOCs (ADC trigger)
EPwm1Regs.ETSEL.bit.SOCBEN = 1; // enable SOC B
EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTRU_CMPB; // SOC from CPMB on upcount
EPwm1Regs.ETPS.bit.SOCBPRD = 1; // Generate pulse on 1st event
EDIS;
// ===== run time actions in CLA code: =====
// check for CCM by current measurement at beginning of switch interval
if ((float32)ADC_U_I1 > U_I_START_THRESH_CCM_TIL) {
// start current too high .. turn off immediately
EALLOW;
//EPwm1Regs.TZFRC.bit.DCAEVT2 = 1; // force DCAEVT2 trip condition ... doesn't work, either !!!!!
EPwm1Regs.TZFRC.bit.CBC = 1; // force CBC trip ... doesn't work !!!!!
EDIS;
//Comp1Regs.DACVAL.bit.DACVAL = 0; // turn off immediately via analog comp. (alternative, works fine, but slower than digital path)
}
// controller code etc....
// ...
// --------------------------------------- end ---------------------------------------