TMS320F28377S: Dual-Edge High Resolution Duty Cycle Control

//###########################################################################
//
// FILE:    HRPWM_Duty_SFO_V8_e2e.c
//
// TITLE:   F2837xD Device HRPWM SFO V8 High-Resolution Period
//          (Up-Down Count) example
//!
//! Monitor ePWM6 A/B pins on an oscilloscope.
//! Monitor a different EPWM A/B channels to
//! compare the edge displacement to (any ePWM 1-8 will work).
//!
//! DESCRIPTION:
//!
//! This example has been modified to show dual edge displacement on the A and B
//! channels of EPWM-6.
//!
//!
//! \b int \b SFO(); \n
//! updates MEP_ScaleFactor dynamically when HRPWM is in use
//! updates HRMSTEP register (exists only in EPwm1Regs register space)
//! with MEP_ScaleFactor value
//! - returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255
//!   (Auto-conversion may not function properly under this condition)
//! - returns 1 when complete for the specified channel
//! - returns 0 if not complete for the specified channel
//!
//! This example is intended to explain the HRPWM capabilities. The code can be
//! optimized for code efficiency. Refer to TI's Digital power application
//! examples and TI Digital Power Supply software libraries for details.
//!
//! All ePWM1 -7 all channels will have fine
//! edge movement due to the HRPWM logic
//!
//! =======================================================================
//! NOTE: For more information on using the SFO software library, see the
//! F2837xD High-Resolution Pulse Width Modulator (HRPWM) Reference Guide
//! =======================================================================


//
// Included Files
//
#include "F28x_Project.h"
#include "SFO_V8.h"

//
// Defines
//
#define PWM_CH            9       // # of PWM channels
#define STATUS_SUCCESS    1
#define STATUS_FAIL       0

#define AUTOCONVERT       0       // 1 = Turn auto-conversion ON
                                  // 0 = Turn auto-conversion OFF

//
// Globals
//
Uint16 UpdateFine;
Uint16 DutyFine;
Uint16 status;
Uint16 CMPA_reg_val;
Uint16 CMPAHR_reg_val;
Uint16 CMPB_reg_val;
Uint16 CMPBHR_reg_val;

int MEP_ScaleFactor; // Global variable used by the SFO library
                     // Result can be used for all HRPWM channels
                     // This variable is also copied to HRMSTEP
                     // register by SFO() function.

//
// Array of pointers to EPwm register structures:
// *ePWM[0] is defined as dummy value not used in the example
//
volatile struct EPWM_REGS *ePWM[PWM_CH] =
             {  &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs,
                &EPwm5Regs, &EPwm6Regs, &EPwm7Regs, &EPwm8Regs};

//
// Function Prototypes
//
void HRPWM_Config(int);
void error(void);

//
// Main
//
void main(void)
{
    int i;
    Uint32 temp, temp1;

//
// Step 1. Initialize System Control for Control and Analog Subsystems
// Enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    EALLOW;
    InitSysCtrl();
    EDIS;

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
   InitEPwmGpio();   // EPWM1A  EPWM1B  through EPWM9
   DINT; // Disable CPU interrupts

//
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
   InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
   EALLOW;
   IER = 0x0000;
   IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
   InitPieVectTable();

//
// For this example, only initialize the ePWM
// Step 5. User specific code, enable interrupts:
//
   UpdateFine = 1;
   DutyFine = 0;
   status = SFO_INCOMPLETE;

//
// Enable global Interrupts and higher priority real-time debug events:
//
   EINT;   // Enable Global interrupt INTM
   ERTM;   // Enable Global realtime interrupt DBGM

//
// Calling SFO() updates the HRMSTEP register with calibrated MEP_ScaleFactor.
// HRMSTEP must be populated with a scale factor value prior to enabling
// high resolution period control.
//
   while(status == SFO_INCOMPLETE)
   {
        status = SFO();
        if(status == SFO_ERROR)
        {
            error();   // SFO function returns 2 if an error occurs & # of MEP
        }              // steps/coarse step exceeds maximum of 255.
   }

//
// ePWM and HRPWM register initialization
//
   EALLOW;
   CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
   EDIS;
   HRPWM_Config(20);   // ePWMx target
   EALLOW;
   CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
   EALLOW;

   // Run SFO for calibration
   status = SFO(); // in background, MEP calibration module
                   // continuously updates MEP_ScaleFactor

   if (status == SFO_ERROR)
   {
       error();   // SFO function returns 2 if an error occurs & #
                  // of MEP steps/coarse step
   }              // exceeds maximum of 255.
   for(;;)
   {

       // Modify CMPAHR register here to see EPWM6 A channel displacement
       // Modify CMPBHR register here to see EPWM6 B channel displacement
    } // end infinite for loop
}

//
// HRPWM_Config - Configures all ePWM channels and sets up HRPWM
//                on ePWMxA / ePWMxB  channels
//
void HRPWM_Config(period)
{
    Uint16 j;

    //
    // ePWM channel register configuration with HRPWM
    // ePWMxA / ePWMxB toggle low/high with MEP control on Rising edge
    //
    for (j=1;j<PWM_CH;j++)
    {
        (*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW;  // set Immediate load
        (*ePWM[j]).TBPRD = period-1;             // PWM frequency = 1 / period
        (*ePWM[j]).CMPA.bit.CMPA = period / 2;   // set duty 50% initially
        (*ePWM[j]).CMPA.bit.CMPAHR = (1 << 8);   // initialize HRPWM extension
        (*ePWM[j]).CMPB.bit.CMPB = period / 2;   // set duty 50% initially
        (*ePWM[j]).CMPB.all |= (1 << 8);         // initialize HRPWM extension
        (*ePWM[j]).TBPHS.all = 0;
        (*ePWM[j]).TBCTR = 0;

        (*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
        (*ePWM[j]).TBCTL.bit.PHSEN = TB_DISABLE;
        (*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
        (*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
        (*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1;
        (*ePWM[j]).TBCTL.bit.FREE_SOFT = 11;

        (*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
        (*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
        (*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
        (*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;


//        (*ePWM[j]).AQCTLA.bit.ZRO = AQ_SET;      // PWM toggle high/low
        (*ePWM[j]).AQCTLA.bit.CAU = AQ_SET;
        (*ePWM[j]).AQCTLA.bit.CAD = AQ_CLEAR;
        (*ePWM[j]).AQCTLB.bit.CBU = AQ_SET;
        (*ePWM[j]).AQCTLB.bit.CBD = AQ_CLEAR;

        if(j == 6)
        {
            EALLOW;
            (*ePWM[j]).HRCNFG.all = 0x0;
            (*ePWM[j]).HRCNFG.bit.EDGMODE = HR_BEP;  // MEP control on falling edge
            (*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP;
            (*ePWM[j]).HRCNFG.bit.HRLOAD  = HR_CTR_ZERO;
            (*ePWM[j]).HRCNFG.bit.EDGMODEB = HR_BEP; // MEP control on falling edge
            (*ePWM[j]).HRCNFG.bit.CTLMODEB = HR_CMP;
            (*ePWM[j]).HRCNFG.bit.HRLOADB  = HR_CTR_ZERO;
            #if (AUTOCONVERT)
            (*ePWM[j]).HRCNFG.bit.AUTOCONV = 1;      // Enable auto-conversion
                                                     // logic
            #endif
            (*ePWM[j]).HRPCTL.bit.HRPE = 0; // Turn off high-resolution period
                                            // control.
            (*ePWM[j]).CMPA.bit.CMPAHR = 0x3333;
            (*ePWM[j]).CMPB.bit.CMPBHR = 0x5555;
            EDIS;
        }

    }
}

//
// error - Halt debugger when called
//
void error (void)
{
    ESTOP0;         // Stop here and handle error
}

//
// End of file
//

//###########################################################################
//
// FILE:    HRPWM_Duty_SFO_V8_e2e.c
//
// TITLE:   F2837xD Device HRPWM SFO V8 High-Resolution Period
//          (Up-Down Count) example
//!
//! Monitor ePWM6 A/B pins on an oscilloscope.
//! Monitor a different EPWM A/B channels to
//! compare the edge displacement to (any ePWM 1-8 will work).
//!
//! DESCRIPTION:
//!
//! This example has been modified to show dual edge displacement on the A and B
//! channels of EPWM-6.
//!
//!
//! \b int \b SFO(); \n
//! updates MEP_ScaleFactor dynamically when HRPWM is in use
//! updates HRMSTEP register (exists only in EPwm1Regs register space)
//! with MEP_ScaleFactor value
//! - returns 2 if error: MEP_ScaleFactor is greater than maximum value of 255
//!   (Auto-conversion may not function properly under this condition)
//! - returns 1 when complete for the specified channel
//! - returns 0 if not complete for the specified channel
//!
//! This example is intended to explain the HRPWM capabilities. The code can be
//! optimized for code efficiency. Refer to TI's Digital power application
//! examples and TI Digital Power Supply software libraries for details.
//!
//! All ePWM1 -7 all channels will have fine
//! edge movement due to the HRPWM logic
//!
//! =======================================================================
//! NOTE: For more information on using the SFO software library, see the
//! F2837xD High-Resolution Pulse Width Modulator (HRPWM) Reference Guide
//! =======================================================================


//
// Included Files
//
#include "F28x_Project.h"
#include "SFO_V8.h"

//
// Defines
//
#define PWM_CH            9       // # of PWM channels
#define STATUS_SUCCESS    1
#define STATUS_FAIL       0

#define AUTOCONVERT       0       // 1 = Turn auto-conversion ON
                                  // 0 = Turn auto-conversion OFF

//
// Globals
//
Uint16 UpdateFine;
Uint16 DutyFine;
Uint16 status;
Uint16 CMPA_reg_val;
Uint16 CMPAHR_reg_val;
Uint16 CMPB_reg_val;
Uint16 CMPBHR_reg_val;

int MEP_ScaleFactor; // Global variable used by the SFO library
                     // Result can be used for all HRPWM channels
                     // This variable is also copied to HRMSTEP
                     // register by SFO() function.

//
// Array of pointers to EPwm register structures:
// *ePWM[0] is defined as dummy value not used in the example
//
volatile struct EPWM_REGS *ePWM[PWM_CH] =
             {  &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs,
                &EPwm5Regs, &EPwm6Regs, &EPwm7Regs, &EPwm8Regs};

//
// Function Prototypes
//
void HRPWM_Config(int);
void error(void);

//
// Main
//
void main(void)
{
    int i;
    Uint32 temp, temp1;

//
// Step 1. Initialize System Control for Control and Analog Subsystems
// Enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    EALLOW;
    InitSysCtrl();
    EDIS;

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
   InitEPwmGpio();   // EPWM1A  EPWM1B  through EPWM9
   DINT; // Disable CPU interrupts

//
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
   InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
   EALLOW;
   IER = 0x0000;
   IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
   InitPieVectTable();

//
// For this example, only initialize the ePWM
// Step 5. User specific code, enable interrupts:
//
   UpdateFine = 1;
   DutyFine = 0;
   status = SFO_INCOMPLETE;

//
// Enable global Interrupts and higher priority real-time debug events:
//
   EINT;   // Enable Global interrupt INTM
   ERTM;   // Enable Global realtime interrupt DBGM

//
// Calling SFO() updates the HRMSTEP register with calibrated MEP_ScaleFactor.
// HRMSTEP must be populated with a scale factor value prior to enabling
// high resolution period control.
//
   while(status == SFO_INCOMPLETE)
   {
        status = SFO();
        if(status == SFO_ERROR)
        {
            error();   // SFO function returns 2 if an error occurs & # of MEP
        }              // steps/coarse step exceeds maximum of 255.
   }

//
// ePWM and HRPWM register initialization
//
   EALLOW;
   CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
   EDIS;
   HRPWM_Config(20);   // ePWMx target
   Init_EPWM();
   EALLOW;
   CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
   EALLOW;

   // Run SFO for calibration
   status = SFO(); // in background, MEP calibration module
                   // continuously updates MEP_ScaleFactor

   if (status == SFO_ERROR)
   {
       error();   // SFO function returns 2 if an error occurs & #
                  // of MEP steps/coarse step
   }              // exceeds maximum of 255.
   for(;;)
   {

       // Modify CMPAHR register here to see EPWM6 A channel displacement
       // Modify CMPBHR register here to see EPWM6 B channel displacement
    } // end infinite for loop
}

//
// HRPWM_Config - Configures all ePWM channels and sets up HRPWM
//                on ePWMxA / ePWMxB  channels
//
void HRPWM_Config(period)
{
    Uint16 j;

    //
    // ePWM channel register configuration with HRPWM
    // ePWMxA / ePWMxB toggle low/high with MEP control on Rising edge
    //
    for (j=2;j<PWM_CH;j++)
    {
        (*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW;  // set Immediate load
        (*ePWM[j]).TBPRD = period-1;             // PWM frequency = 1 / period
        (*ePWM[j]).CMPA.bit.CMPA = period / 2;   // set duty 50% initially
        (*ePWM[j]).CMPA.bit.CMPAHR = (1 << 8);   // initialize HRPWM extension
        (*ePWM[j]).CMPB.bit.CMPB = period / 2;   // set duty 50% initially
        (*ePWM[j]).CMPB.all |= (1 << 8);         // initialize HRPWM extension
        (*ePWM[j]).TBPHS.all = 0;
        (*ePWM[j]).TBCTR = 0;

        (*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
        (*ePWM[j]).TBCTL.bit.PHSEN = TB_DISABLE;
        (*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
        (*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
        (*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1;
        (*ePWM[j]).TBCTL.bit.FREE_SOFT = 11;

        (*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
        (*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
        (*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
        (*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;


//        (*ePWM[j]).AQCTLA.bit.ZRO = AQ_SET;      // PWM toggle high/low
        (*ePWM[j]).AQCTLA.bit.CAU = AQ_SET;
        (*ePWM[j]).AQCTLA.bit.CAD = AQ_CLEAR;
        (*ePWM[j]).AQCTLB.bit.CBU = AQ_SET;
        (*ePWM[j]).AQCTLB.bit.CBD = AQ_CLEAR;

//        if(j == 6)
//        {
//            EALLOW;
//            (*ePWM[j]).HRCNFG.all = 0x0;
//            (*ePWM[j]).HRCNFG.bit.EDGMODE = HR_BEP;  // MEP control on falling edge
//            (*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP;
//            (*ePWM[j]).HRCNFG.bit.HRLOAD  = HR_CTR_ZERO;
//            (*ePWM[j]).HRCNFG.bit.EDGMODEB = HR_BEP; // MEP control on falling edge
//            (*ePWM[j]).HRCNFG.bit.CTLMODEB = HR_CMP;
//            (*ePWM[j]).HRCNFG.bit.HRLOADB  = HR_CTR_ZERO;
//            #if (AUTOCONVERT)
//            (*ePWM[j]).HRCNFG.bit.AUTOCONV = 1;      // Enable auto-conversion
//                                                     // logic
//            #endif
//            (*ePWM[j]).HRPCTL.bit.HRPE = 0; // Turn off high-resolution period
//                                            // control.
//            (*ePWM[j]).CMPA.bit.CMPAHR = 0x3333;
//            (*ePWM[j]).CMPB.bit.CMPBHR = 0x5555;
//            EDIS;
//        }

    }
}

void Init_EPWM(void)
{
   //
   // Setup TBCLK
   //
   //NOTE: The EPWM module for this processor has a built in hardware limitation on clock frequency of 60MHz to 100MHz for full functionality.
   //To handle this, an integer /2 of the main CPU clock is enabled by default in the register ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV
   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
   EPwm1Regs.TBPRD = 19;       // Set timer period
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;// Used as sync signal for phase locked PWMs
   EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
   EPwm1Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

   //
   // Setup shadow register load on ZERO
   //
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   //
   // Set Compare values
   //
   EPwm1Regs.CMPA.bit.CMPA = 20 / 2;   // set duty 50% initially
   EPwm1Regs.CMPB.bit.CMPB = 20 / 2;   // set duty 50% initially
   EPwm1Regs.CMPA.bit.CMPAHR = (1 << 8);
//   EPwm1Regs.CMPB.bit.CMPB = 0;             // Set Compare B value
   EPwm1Regs.CMPB.bit.CMPBHR = (1 << 8);
//   EPwm1Regs.CMPC = EPWM_ADC_SOC_COUNT;     // Set Compare C value
//   EPwm1Regs.CMPD = EPWM_INTERRUPT_COUNT;   // Set Compare D value

   //
   // Set actions
   //
   EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;            // Set PWM1A on Zero
   EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;    // Clear PWM1A on event A,
                                                 // up count

   EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;            // Set PWM1B on Zero
   EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;          // Clear PWM1B on event B,
                                                 // up count
   //
   // Setup Deadband (assumes non-inverted gate drive signals and EPWMxA as the source for both delays)
   // Presently creating dead band programmatically.  May need to use external deadband circuit to "steal" pulse width
   // That will allow the PWM module to stay in the (3, PERIOD-3) window at effective zero pulse width
   //
   /*EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
   EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
   EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
   EPwm1Regs.DBRED.bit.DBRED = 0x00A;   //100MHz EPWMCLK => 10ns per count, assume 100ns dead band to start
   EPwm1Regs.DBFED.bit.DBFED = 0x00A;   //100MHz EPWMCLK => 10ns per count, assume 100ns dead band to start*/

   //
   // Interrupt where we will change the Compare Values
   //
   EPwm1Regs.ETSEL.bit.INTSELCMP = 1;              // Select alternate compare source i.e. CMPC/CMPD
   EPwm1Regs.ETSEL.bit.INTSEL = ET_CTRD_CMPB;     // Select INT on CMPD down count
   EPwm1Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 1st event

   //
   // Configure ADC SOCA signal
   //
   EPwm1Regs.ETSEL.bit.SOCASELCMP = 1;           //Use CMPC as ADC SOCA source
   EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTRU_CMPA;   //ADC SOCA sent out on CMPC incrementing edge
   EPwm1Regs.ETSEL.bit.SOCAEN = 1;
   EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;

   //
   //Configure High-Resolution PWM Registers
   //
   EALLOW;
   EPwm1Regs.HRCNFG.all = 0x0;
   EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP;
   EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
   EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
   EPwm1Regs.HRCNFG.bit.EDGMODEB = HR_BEP;
   EPwm1Regs.HRCNFG.bit.CTLMODEB = HR_CMP;
   EPwm1Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO;
   EPwm1Regs.HRCNFG.bit.AUTOCONV = 0;
   EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1;
   EPwm1Regs.HRPCTL.bit.HRPE = 1;
   EPwm1Regs.CMPA.bit.CMPAHR = 0x3333;
   //            (*ePWM[j]).CMPB.bit.CMPBHR = 0x5555;
//   CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
//   EPwm1Regs.TBCTL.bit.SWFSYNC = 1;
   EDIS;

   //
   // Configure Trip-Zone Module Registers
   //
   EALLOW;
   EPwm1Regs.TZCTL.all = 0xFFFF;
#if HI_RES_CTRL
   EPwm1Regs.TZSEL.bit.CBC1 = TZ_ENABLE;        //Enable cycle by cycle trip zone functionality
   EPwm1Regs.TZCLR.bit.CBCPULSE = 0;            //Have cycle by cycle trip clear at zero count, unless the signal persists.
   EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
   EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
#endif
   EDIS;
}
//
// error - Halt debugger when called
//
void error (void)
{
    ESTOP0;         // Stop here and handle error
}

//
// End of file
//