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TMS320F28374S: Issue with PWM unit using dead band module and 100% / 0% duty cycle

Jens Kaufmann1
Intellectual 280 points
Part Number: TMS320F28374S

We produce the PWM signals for a buck – boost stage with a PWM unit of the C2000 F28374 using the dead band module.

 

While testing the PWM operation in its extreme points (start / stop, 100% / 0% dutycycle, different dead band settings etc.) I discovered a for me none plausible behavior.

 

The PWM unit is configured in a way, that signal A and B have the same action qualifiers on CMPA while signal B gets inverted over the dead band module. RED can be applied to Signal A, FED to singal B.


In 0% duty cycle operation Signal A is high and signal B is low, vice versa in 100% duty cycle.

 

Changing the duty cycle to 0% while RED is 0 and then increasing RED to e.g. 100ns forces Output A to low. This only happens when RED has been 0 before the duty cycle change. That means that changing the duty cycle to 0 with RED = 100ns and then changing RED to 0 and back to 100ns works as expected (Output A stays high).

 

Same thing happens on Output B in 100% duty cycle operation when changing FED.

 

 

Of course using dead times for 100 or 0% duty cycle does not make sense and probably we never see this scenario as we have minimum allowed dead times so no one could set FED / RED to 0 in normal operation. Anyway my claim is understanding the configuration and the resulting behavior of the PWM unit to 100% in all theoretical possible operating conditions.

 

Are there any explanations for this behavior?

 

Below you can find our configuration routines:

 

Configuration of PWM unit:

 

void PWMConfigBooster(volatile struct EPWM_REGS *EPWM)

{

       EPwm1Regs.TBCTL.bit.CTRMODE                    = TB_COUNT_UPDOWN; // Asymmetrical mode

       EPwm1Regs.TBPRD                                       = PWM_50KHZ_PRD_CNTUPDOWN; // Period = 900 TBCLK counts

 

       EPwm1Regs.TBPHS.bit.TBPHS               = 0;                       // Set Phase register to zero

 

       EPwm1Regs.TBCTL.bit.PHSEN               = TB_DISABLE;       // disable phase sync as booster pwm is Master

       EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE       = 0;

       EPwm1Regs.TBCTL.bit.SYNCOSEL                   = TB_CTR_ZERO;             // Sync out to all slaves

       EPwm1Regs.TBCTL.bit.PHSDIR                     = 1;                       // count up after SYNC event and the new value of the phase (TBPHS) is loaded.

       EPwm1Regs.TBPHS.bit.TBPHS               = 0;                       // initial - coarse phase offset relative to ePWM1

 

       EPwm1Regs.TBCTL.bit.PRDLD               = TB_SHADOW;

       EPwm1Regs.TBCTL.bit.HSPCLKDIV           = TB_DIV1;                 // Prescaler = 1

       EPwm1Regs.TBCTL.bit.CLKDIV                     = TB_DIV1;         // TBCLK = SYSCLKOUT

 

       EPwm1Regs.CMPCTL.bit.SHDWAMODE          = CC_SHADOW;

       EPwm1Regs.CMPCTL.bit.SHDWBMODE          = CC_SHADOW;

 

       EPwm1Regs.CMPCTL.bit.LOADAMODE          = CC_CTR_ZERO;      // load on CTR=Zero

       EPwm1Regs.CMPCTL.bit.LOADBMODE          = CC_CTR_ZERO;      // load on CTR=Zero

 

       StopBoosterPWM();

 

       EPwm1Regs.AQCTL.bit.SHDWAQAMODE         = 1;         //enable shadow loading for action qualifier A register

       EPwm1Regs.AQCTL.bit.SHDWAQBMODE         = 1;         //enable shadow loading for action qualifier B register

 

       //configure deadband module to use rising edge delay on output A and to invert output B

       //see DeadBandModuleConfigHssPwms.png for more details

       EPwm1Regs.DBCTL.bit.IN_MODE       = 0x2; // EPWMxA is the source for rising-edge delay, EPWMxB for falling-edge delay. (S4 = 0, S5 = 1)

       EPwm1Regs.DBCTL.bit.DEDB_MODE = 0x0;    // S8 = 0

       EPwm1Regs.DBCTL.bit.POLSEL        = 0x2;       // invert ePWMxB signal coming out of falling edge delay block (S2 = 0, S3 = 1)

       EPwm1Regs.DBCTL.bit.OUT_MODE      = 0x3;       // enable Dead-band module for EPWMxA and EPWMxB signals (S0 and S1 = 1)

       EPwm1Regs.DBCTL.bit.OUTSWAP      = 0x0; // S6 and S7 = 0

 

       EPwm1Regs.DBFED.bit.DBFED         = PWM_DEADTIME_IN_TICKS;   // FED = 50 TBCLKs initially

       EPwm1Regs.DBRED.bit.DBRED         = PWM_DEADTIME_IN_TICKS;   // RED = 50 TBCLKs initially

 

}

 

Function to stop PWM

void StopBoosterPWM(void)

{

#ifdef SET_HSS_PWM_STOP_GPIO

       SET_HSS_PWM_STOP_GPIO

#endif

       EPwm1Regs.AQCTLA.bit.CAU                       = AQ_CLEAR;

       EPwm1Regs.AQCTLA.bit.CAD                       = AQ_CLEAR;

 

       EPwm1Regs.AQCTLB.bit.CAU                       = AQ_SET;   //signal gets inverted in the deadband module

       EPwm1Regs.AQCTLB.bit.CAD                       = AQ_SET;    //signal gets inverted in the deadband module

 

#ifdef CLEAR_HSS_PWM_START_GPIO

       CLEAR_HSS_PWM_START_GPIO

#endif

}

 

Function to start PWM

void StartBoosterPWM(void)

{

#ifdef SET_HSS_PWM_STOP_GPIO

       SET_HSS_PWM_STOP_GPIO

#endif

       EPwm1Regs.AQCTLA.bit.CAU                       = AQ_CLEAR;

       EPwm1Regs.AQCTLA.bit.CAD                       = AQ_SET;

 

       EPwm1Regs.AQCTLB.bit.CAU                       = AQ_CLEAR; //signal gets inverted in the deadband module

       EPwm1Regs.AQCTLB.bit.CAD                       = AQ_SET;   //signal gets inverted in the deadband module

#ifdef CLEAR_HSS_PWM_STOP_GPIO

       CLEAR_HSS_PWM_STOP_GPIO

#endif

}

Thanks!

Jens

  • 0
    TI__Genius 17370 points
    please check if the discussions at e2e.ti.com/.../273846 helps

    Regards
    Baskaran
  • 0 in reply to Baskaran Chidambaram
    Intellectual 280 points

    Hi Baskaran,

    I already went through the suggested post and this is not the same issue I have seen. For our application it is not critical when the FED/RED changes take impact on the output signals.

    What I have seen is that changing RED from 0 to a higher value in 0% duty cycle operation forces output A from constantly high to constantly low. Same thing with FED and output B in 100% duty cycle operation.

    In my opinion there shouldn't be any edges or changes of the output signals in 0% or 100% duty cycle operation.

    As I mentioned this behavior is only seen if RED/FED had been 0 when entering 0%/100% duty cycle operation. If RED/FED had been for example 100ns when entering 0%/100% duty cycle operation and then get set to 0 and back to other values everything works like expected (output signals stay constant).

    Thanks

    Jens

  • 0 in reply to Jens Kaufmann1
    Genius 5885 points

    When reading this keep in mind that I do not know the internal structure of the dead band module and my recommendations are based only on practical experiences and from discussions on E2E forum. Also the operation of dead band module differs on the silicon used and I've got most experiences with 28069

    Dead time module is not really intended for on line reconfiguration. As the internal compare registers are not shadowed so you might observe strange phenomena when changing RED of FED values or othre DB configuration registers. This phenomena might appear sporadic or even random in nature but the underlying cause is the timing of the write to the DB module with respect to the internal counters.

    My advice for the projects where you need to vary dead time is to disable dead time module and use AQ module with comparator A and comparator B to generate dead time (look at the example on figure 14-29 on page 1585 in SPRUHM8F)

  • 0 in reply to Mitja Nemec
    Intellectual 280 points

    Hi Mitja,

    thanks for your feedback.

    We moved from the 28069 to 28374S and one thing to notice regarding online reconfiguration of the dead band module is, that the newer devices with generation 4 PWM unit have an optional shadow registers for RED and FED writes. Therefore I assume that I'm allowed to change RED/FED values online, otherwise those shadow registers do not make sense to me.

    After your answer I rechecked my configuration and saw that I did not use the shadow registers for FED and RED. Unfortunately after changing the configuration to use them, I can see the same behavior as before.

    Can anyone of TI confirm that changing RED and FED registers online is allowed?

    Thanks

    Jens

  • 0 in reply to Jens Kaufmann1
    Genius 5885 points

    Thanks for the update. It seems that with each new generation you really have to scan through all the documentation again, to catch small changes.

    On thing I would try is to change RED and FED from 1 to higher value and back, instead of going to and from 0. This might be similar issue that old ePWM modules had when setting CMPA to 0 or to PRD as the could not generate 0% and 100% duty on PWM signal.

    As for the TI support, I doubt you will get an response

  • 0 in reply to Mitja Nemec
    TI__Genius 15260 points

    Hi Jens,

    There should not be a problem with online changing of the deadband registers. Is this still an ongoing issue that you would like us to try to reproduce?

    Regards,

    Kris

  • 0 in reply to Kris Parrent
    Intellectual 280 points

    Hi Kris,

    it would be great if you could try to reproduce this issue as I want to make sure that I didn't configure anything wrong.

    Thanks

    Jens

  • 0 in reply to Jens Kaufmann1
    TI__Genius 15260 points
    Jens,

    Sure, I am working on getting your code into an example and will get back to you with results.

    Regards,
    Kris