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CCS/TMS320F28379D: How to control the SPI STE (Chip Select) output and SPI transactions longer than 16 bits?

Graham Reitz29
Intellectual 960 points
Part Number: TMS320F28379D

Tool/software: Code Composer Studio

Hello,

I am writing a driver for the WIZnet W5500 SPI to ethernet converter.  (Side note*:  I didn't see an offering from TI to add ethernet functionality with a complete IP stack to the F2837x conrtolCard.)

The WIZnet utilizes a 24 bit + N data bytes SPI protocol.  It requires that the CS pin (I'm assuming that TI calls this the SPISTE) be controlled by the master, the controlCard, for data reads/writes.

I have two issues:

1) How can the STE (CS) be controlled?  It looks like it's controlled automatically at the moment.

2) The TI SPI software interface uses Uint16 data types.  The minimum SPI transaction with the WIZNet device is 32 bits.  Do I need to write a 32 bit version or can the TI SPI software interface be used?

Kindly,

Graham

  • 0
    TI__Genius 15260 points

    Hi Graham,

    The SPISTE is controlled automatically. For back to back transactions it will stay active though, so one option may be back-to-back transactions to total 24 + N bits.

    Another option is to use a GPIO to emulate the SPISTE signal if you want to manually control it. Just toggle the GPIO low before the transaction and toggle it high when you have completed.

    Regards,
    Kris

  • 0 in reply to Kris Parrent
    Intellectual 960 points
    Thanks Kris,

    I will try that technique.

    Could you request that the TI SPI engineers update the C++ interface to include the ability to set the bit width in a future release? Limiting it to 16-bits is unfortunate, given the plethora of SPI applications that use bit lengths other than 16.

    Kindly,
    Graham