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TMS320F28075: Type 4 EPWM to Generate Full Range 0~100% Duty Cycle Waveform w/o ISR Intervention

Ricky Zhang
Genius 9520 points
Part Number: TMS320F28075

Hi, Champs,

As described in F28075 TRM, users need to follow Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100% Duty Cycle Control Application Report (literature number SPRAAI1)  to output 0~100% duty cycle waveform.

However, test results show difference between type 0 EPWM and type 4 EPWM on this.

Taking an example as below, CMPA is used to make the comparison, and EPWM will load its shadow to active at TBCTR=0:

 - When the counter is incrementing the CMPA match will pull the PWM output high, i.e. EPwmxRegs.AQCTLA.bit.CAU = AQ_SET;

 - When the counter is decrementing the CMPA match will pull the PWM signal low, i.e. EPwmxRegs.AQCTLA.bit.CAU = AQ_CLEAR;

Basically, when CMPA is a non-zero value, EPWM will output waveform with duty cycle falls into range of 0%<duty cycle<100%, and if users want to output 100% duty cycle or all high within period, CMPA will be changed to 0 from a non-zero value, while there're two scenarios on different device families.

On type 0 EPWM, like device F2808, it seems CMPA will be loaded as 0 once TBCTR=0, and then the comparison action will be ignored thus CAU event will NOT occur so output high will not work, just like documented in TRM as below:

There are some cases when the action based on the new value can be delayed by one period or the action based on the old value can take effect for an extra period.

However, on type 4 EPWM, like device F28075, it seems to be another case. CMPA will be loaded as 0 as soon as TBCTR reaches 0, and then the comparison action will take effect immediately to generate CAU event for pulling EPWM output to high.

That means, we can output full range 0~100% duty cycle with type 4 EPWM without ISR intervention, however, there're still questions need to check.

Could you please confirm if my understanding is correct or not for above yellow highlighted statement?

And could you please help to review design details on which modification had been made to guarantee this (update CMPA=0 first and compare match second at TBCTR=0)?

If it's true, then perhaps we will also need to revise the chapter 13.6.5 Waveforms for Common Configurations on TRM.

My customer is testing this and hopefully they can use this approach in their real application to save a 2us codes execution in their ISR for this purpose, however, they have no confidence as F2808 can not support this, and they don't know if it's reliable on F28075, so it's important to show them the changes we have made and convince them from design perspective.

Thanks for your support.

Best Regards,

Ricky Zhang

  • 0
    TI__Mastermind 41515 points

    Ricky, your findings are correct.

    On devices like F2808 and F2833x (Type0 PWM) when loading 0 on TBCTR=0 the event will be missed for one PWM period and thus the AQ needs to be used to force the PWM low. This is described in SPRAAI1.

    On newer devices like F2807x( anything Type 1,2,3,4) the shadow load occurs before CMPA is compared to TBCTR. This is closed with design and will always happen.

    How does the workaround affect newer devices? For newer devices you only need to worry about Up-down count mode. As described before CMPA =0 will not be missed. However, when switching from a CMPA =0  to a non-zero CMPA the workaround is still suggested to be used.

    Regards,
    Cody  

  • 0 in reply to Cody Watkins
    TI__Genius 9520 points

    Cody,

    Thanks for your quick response and confirmation on my understanding.

    Cody Watkins said:

    On newer devices like F2807x( anything Type 1,2,3,4) the shadow load occurs before CMPA is compared to TBCTR. This is closed with design and will always happen.

    As my further question in the original post, could you please help to review design details on which modification had been made to guarantee this (update CMPA=0 first and compare match second at TBCTR=0)? Any internal block diagram or circuit for this change would be helpful for us to convince customer as they still have concern on its reliability.

    Cody Watkins said:

    How does the workaround affect newer devices? For newer devices you only need to worry about Up-down count mode. As described before CMPA =0 will not be missed. However, when switching from a CMPA =0  to a non-zero CMPA the workaround is still suggested to be used.

    Yes, I see. Actually I have written all the test code for customer and handled this special scenario, i.e. pull the output to low on ZRO event with configuration EpwmxRegs.AQCTLA.bit.ZRO = AQ_CLEAR, and I switched all 6 possible cases with correct results.

    Best Regards,

    Ricky Zhang

  • 0 in reply to Ricky Zhang
    TI__Mastermind 41515 points
    Ricky,
    I'm glad to see you have this working. This design is well tested and has been known to function reliably. I don't have a block diagram, but if you look at the TRM Figure 13-24 documents the 0% duty case for up-down count mode.

    Please let me know if this figure is insufficient and I will try to find you more reference materials.

    Regards,
    Cody
  • 0 in reply to Cody Watkins
    TI__Genius 9520 points

    Cody,

    I'm afraid this is not what we're looking for since there's below statement above the figure you mentioned, which means the limitation is still existed:

    When using this configuration in practice, if you load CMPA/CMPB on zero, then use CMPA/CMPB values greater than or equal to 1. If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or equal to TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period which, when very short, tend to be ignored by the system.

    Actually if you take a look at F280x EPWM user guide (SPRU791F), there's identical waveform and statements (Figure 2-20), so I'm afraid we simply copied it from early version EPWM user guide to new, however, customer will just take it as correct and F2807x type 4 EPWM will behave exactly the same as F280x type 0 EPWM on this feature, so extra block diagram or documents will still be required to show their difference.

    Best Regards,

    Ricky Zhang

  • 0 in reply to Ricky Zhang
    TI__Genius 9520 points

    Cody,

    Could you please help to confirm this as well and let me know if we can find any docs or block diagram to share on this slight change?

    I guess Hrishi or Alex would have something regard to it?

    Best Regards,

    Ricky Zhang