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Tool/software: Code Composer Studio
hello everyone:
I have a question about CAN receive interrupt. In my program, CAN mailboxes 16 to 31 are set to receive mailboxes.After the program has been running for more than 5 hours, it can't enter CAN interrupt, RMP and RML receiving mailboxes are all 1 and CANGIF0.MIV0 stays at 31.Who knows what the reason is, thank you.
Thanks, I have read these values. They have no problem. The problem I have now is that after the program runs for 354 minutes, when the CAN enters the receive interrupt, after the mailbox 31 receives the data, the remaining mailboxes will not receive data. At this time, RMP and RML are both set. CAN cannot run to ECanaRegs.CANRMP.all = 0xFFFF0000, so RMP and RML cannot be cleared; my program is mainly used to generate PWM wave, switching frequency is 15K.
interrupt void CAN0A_intISR(void)
{
volatile Uint16 TempPIEIER;
Uint16 i;
TempPIEIER = PieCtrlRegs.PIEIER9.all; // Save PIEIER register for later
IER |= M_INT9; // Set global priority by adjusting IER
IER &= 0x0104;
PieCtrlRegs.PIEIER3.all &= 0x0001; // Set group priority by adjusting PIEIER2 to allow INT2.2 to interrupt current ISR
PieCtrlRegs.PIEACK.all = 0xFFFF; // Enable PIE interrupts
asm(" NOP"); // Wait one cycle
EINT;
if(ECanaRegs.CANGIF0.bit.MIV0 == 16)
{
for(CAN_read=0;CAN_read<=15;CAN_read++)
{
mailbox_read(CAN_read+16); // This func reads the indicated mailbox data
CAN_Recei[CAN_read][0]=TestMbox1;
CAN_Recei[CAN_read][1]=TestMbox2;
}
gCAN_recei_CAN();
bzw = 1;
bzw_CANjiance =0;
zdjs++;
zdjs1++;
if(zdjs == 1)
{
P_CheckSet();
P_GetSetFromRam();
}
if(zdjs >=2)
{
zdjs =2;
}
}
ECanaRegs.CANRMP.all = 0xFFFF0000;
PieCtrlRegs.PIEACK.bit.ACK9 = 1;
EINT;
for(i = 1; i <= 10; i++) {}
DINT;
PieCtrlRegs.PIEIER9.all = TempPIEIER;
}
If the acceptance mask filtering criterion is satisfied (or exact ID match if filtering is not used), the message must be received in the corresponding mailbox. There is no way a valid message fails to be received in the appropriate mailbox.
The various bits at play for an interrupt to be recognized are clearly shown in Fig 83 (page 121 of SPRUFB0D). The steps also clearly explain the sequence.
You need to use 32-bit R/W as stated in the CAN User Guide. See 1.3.2.1 in page 15 of SPRUEU1. This line violates that stipulation: ECanaRegs.CANGIF0.bit.MIV0 == 16
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