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Tool/software: TI C/C++ Compiler
Hi
I'm having a problem with code hitting ISR_ILLEGAL trap. This started to happen after a code change, but the change isn't that closely related to the place where the illegal isr is triggered. After debugging this for quite some time I'm suspecting I'm experiencing the "Prefetching Beyond Valid Memory" errata.
I have plenty of stack left and increasing stack size doesn't help. So, I think it's not a stack overflow problem. It seems the illegal isr gets triggered from a function where I'm using DELAY_US macro. If I step through the code it works. DSP28x_usDelay is executed from ram and ramfuncs is stored in RAML1. DSP28x_usDelay is the last function in RAML1 which is almost full: 1020 of 1024 (99%) used. The last 8 words of the memory region are not unused as the errata suggests. Freeing up space in RAML1 fixes the problem.
My doubt in this is that it's very easy to fix/lose the problem with some other change which doesn't affect RAML1 in any way. Would this indicate that my assumption is wrong, and the real problem is something else?
How can I ensure that the last 8 words of a memory area are left unused? Can it be done from the linker cmd file? If I change the length of RAML1 from 0x000400 to 0x0003F8 will it do the trick or will the prefetch problem happen just earlier in the memory?
Or can it be done on the sections level? Since prefetching over the memory block boundary is ok, I want to ensure that the last words of the last memory block stay unused when a section is allocated to multiple memory blocks. For example in case:
.text : >> FLASHD | FLASHE | FLASHF, PAGE = 0
Best regards
Pauli
Thank you. I see this was explained in example 2 in the errata, which I somehow misread. However, Could you explain what is meant by "valid RAM". Is it just any memory block regardless from how it is used or should it be program memory?
In my case L2 is used as data memory and contains CLA data variables. So, if the CPU prefetches past the L1 end, into L2 RAM it will fetch some random variable value. Not an valid opcode.
Couldn't find any details about how the prefetch in this processor works.
Now that I think of it, L2 RAM is configured as cla data RAM with the following line:
Cla1Regs.MMEMCFG.bit.RAM1E = 1; // Configure CLA data RAM 1 (L2 RAM) for CLA use
So, I guess it is not "available for CPU usage" and the errata applies?
Best regards
Pauli
Hi Pauli,
"Vaild RAM" means any memory block from where CPU can fetch the code even though the code is invalid. Issue happens if CPU fetch is not allowed or there is no valid memory block the CPU fetch may cause access violation even though CPU is not going to execute that code.
Hope it's clear.
Regards,
Vivek Singh