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TMS320F28379D: HRPWM MEP Step to Step Variance

Eric Best
Expert 7205 points
Part Number: TMS320F28379D

For a given device/HRPWM instance, at fixed voltage and fixed temperature, what is a rough ballpark for typical HRPWM MEP step size variance?  Using SFO, we will have an average step size, represented as a number of steps per one sysclk tick.  Understand that this is not a characterized data manual parameter, just trying to get a rough understanding of what to expect, i.e. +/- 10%, 20%, 40%?  The use case is understanding the absolute delay of say 5 to 10 steps.  If the average value is used, what would be a decent rule of thumb for the error (using SFO based average)?

A side question would be related to voltage sensitivity.  Can a change from 1.2 to 1.15V have a significant impact?  This relates to the assumption of fixed voltage.

  • 0
    TI__Guru 52010 points

    Eric,

    I have to investigate to see if we have data for this.

    Nima

  • 0 in reply to Nima Eskandari
    TI__Guru 52010 points
    I am still awaiting response from HRPWM masters to see if they have any data on this.

    I do believe both voltage and temperature affect the delay added by each element. That is why it is a good idea to periodically call the SFO function to make sure that the scale factor is updated with the change in the device environment.

    Nima
  • 0 in reply to Nima Eskandari
    TI__Guru 52010 points
    After running some test and doing a bit of calculation, a rough estimate for HRPWM step size variation at a given temperature and voltage, is about +/-2%. Again this is a rough estimate. The variation is mostly due to temperature and not the voltage. We do not have a number for HRPWM step size vs. temperature.
  • 0 in reply to Nima Eskandari
    TI__Expert 7205 points

    HI Nima,

    Thanks for digging up this info.  +/- 2% is pretty tight (better than expected tolerance over all process corners).  I assume that this step to step variance is independent of the SFO "average" effect?

    For example, if SFO comes back with 33 steps/Sysclk (10nS), the average is 303pSec.  If SFO comes back with 34 steps/Sysclk tick, the average is 294pSec.  At this end of the range, the SFO average number will be roughly +/- 1.5%.   

    Is the +/-2% number exclusive or inclusive of the SFO average error?  In other words, is the +/-2% based on actual process data and not based on the usage of a SFO determined average step size (as would be used in the actual application)?

    Is the +/-2% based on design simulation data? 

    Regards,
    Eric

  • 0 in reply to Eric Best
    TI__Guru 52010 points
    This is NOT based on design simulation data. I am not allowed to share design data. This is based on a small bench measurement the team had. This is data calculated by SFO.