Hi expert,
We are sampling HV DC through voltage divider into ADCs. We met some problem that the divided voltage signal is clamped on some channels (can not go up than 2.2V when increase HV DC, reference is 3.3V) where these pins are connected to multiple ADC inputs such as pin 36 in 100 pin package. But this problem will not happen on pins connected with only one ADC input such as pin 38 in 100 pin package.
We already tested these ADC channels with signal source, everything is fine with a strong source. So we would like to know the reason behind this phenomenon. Did these pins get different input impedence?
We'd like to do some test by directly route signal (divided HV DC) into ADC through PAG_OF pin with ADC input disabled. Is that possible?
Thanks
Sheldon