CCS/TMS320F28379S: Boot mode for 28379S

Hi,

Your configuration is correct for Get mode and to run the code from flash. I hope the code is configured to run from flash and not RAM, right?

Regards,
Gautam

Yes, I want to run my code on flash.

Have you connected and checked the boot up status? That can help determine what is going on.
Additionally, make sure your app is properly set to the entry address in flash.

Best regards
Chris

Chris,

How can I check the boot up status?

My cmd file is as follow

-------------

// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */

BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
/* RAMLS4 : origin = 0x00A000, length = 0x000800 */
/* RAMLS5 : origin = 0x00A800, length = 0x000800 */
RAMLS4_5 : origin = 0x00A000, length = 0x001000

RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RESET : origin = 0x3FFFC0, length = 0x000002

/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */

PAGE 1 :

BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */

RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800

RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
/*
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
*/
RAMGS5_6_7_8 : origin = 0x011000, length = 0x004000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on , F28377S, F28375S devices. Remove line on other devices. */

EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
EMIF1_CS2n : origin = 0x00100000, length = 0x00200000
EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
EMIF2_CS0n : origin = 0x90000000, length = 0x10000000
EMIF2_CS2n : origin = 0x00002000, length = 0x00001000

CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}

SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB PAGE = 0, ALIGN(4)
.pinit : > FLASHB, PAGE = 0, ALIGN(4)
.text : > FLASHB|FLASHC|FLASHD|FLASHE|FLASHF PAGE = 0, ALIGN(4)
codestart : > BEGIN PAGE = 0, ALIGN(4)

/* Allocate uninitalized data sections: */
.stack : > RAMLS3 PAGE = 1
.ebss : > RAMGS5_6_7_8 PAGE = 1
.esysmem : > RAMLS2 PAGE = 1

/* Initalized sections go in Flash */
.econst : > FLASHB PAGE = 0, ALIGN(4)
.switch : > FLASHB PAGE = 0, ALIGN(4)

.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

Filter_RegsFile : > RAMGS0, PAGE = 1

.em2_cs0 : > EMIF2_CS0n, PAGE = 1
.em2_cs2 : > EMIF2_CS2n, PAGE = 1

/* CLA specific sections */
Cla1Prog : LOAD = FLASHD,
RUN = RAMLS4_5,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
PAGE = 0, ALIGN(4)

CLADataLS0 : > RAMLS0, PAGE=0
CLADataLS1 : > RAMLS1, PAGE=0

Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1

/* Digital Controller Library functions */
dclfuncs : > RAMGS10, PAGE = 1
dcl32funcs : > RAMGS11, PAGE = 1

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMD0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
ramfuncs : LOAD = FLASHD,
RUN = RAMD0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
#endif

/* The following section definition are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444

#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 0

.scratchpad : > RAMLS1, PAGE = 0
.bss_cla : > RAMLS1, PAGE = 0
.const_cla : LOAD = FLASHB,
RUN = RAMLS1,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 0
#endif //CLA_C
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Your codestart->BEGIN section looks to be setup and linked to the correct spot.

The ROM status can be read from address 0x2C
This and all other boot details can be found in the TRM chapter: http://www.ti.com/lit/spruhx5

Best regards
Chris

Hello

I haven’t heard from you for a couple weeks, so I’m assuming you were able to resolve your issue. If this isn’t the case, please reject this resolution and reply to this thread with your latest status/update/information. If this thread locks, please click the "Ask a related question" button and in the new thread describe the current status of your issue and any additional details you may have to assist us in helping to solve your issues.

Best regards
Chris

Hi,

Sorry too late reply.

I had tried to solve this issue, but failed.

I left this problem at left side and focused on the development the main code.

The main code has been almost completed, so I have to get back to this problem to solve.

What will "ROM status" be helpful?

Please give me the detail information.

BR

Paul   

Paul

I recommended the ROM status and TRM to help you confirm your boot settings are all correct.

Best regards
Chris

Hi,

I attached Z1/Z2_BOOTCTRL register content.

Flash boot mode is not working.

What do I have to check?

BR

Paul

Paul

Those values look fine and unprogrammed. With those, GPIO72 and 84 pulled high should go to flash boot. When you look at the boot status in RAM (refer to the "Boot Status information" section in the TRM), what does it tell you? Also post the value.
To get the status, get to the device after booting with a target configuration file that doesn't have any GEL (so it doesn't reset the device).

Best regards
Chris

Chris

How can I check my target configuration file does not have any GEL or not?

I attached the boot status information, no concerned with GEL.

I use __attribute__((ramfunc)) director, is it OK for booting with FLASH?

BR

Paul

Paul

Open (or make copy of your target config first) the target config, go to the advanced tab, and select CPU1 in the tree. On the right, clear out the "initialization script" text so it is blank. Click save, now it won't use the GEL. The GEL will perform RAM initialization upon target connect and clear out the boot status (hence why you see zeroes).
I don't think there should be an issue using that director.

Best regards
Chris

Chris,

I have test the on 379D launchpad.

I got as follow.

BR

Paul

Paul

This confirms that it is performing flash boot. It is also indicating that an iTRAP was detected. Do you have code programmed at 0x80000? Your linker looked correct, but iTRAP indication is concerning.
You can also try to debug with debugger connected (first must either set emulation boot to flash or emulation standalone boot option), perform a CPU reset (not restart) in CCS, set breakpoint at 0x80000, run and it should hit it, then you can step.

Best regards
Chris

Chris,

How to do this?

"first must either set emulation boot to flash or emulation standalone boot option), perform a CPU reset (not restart) in CCS"

Paul

Emulation boot data is configured at 0xD00. You can either set it manually (details in the technical reference manual) or after you connect to the device, find the Scripts drop-down at the top of CCS, then"Emu Boot Mode Select" menu, and select EMU_BOOT_FLASH. This will configure the same thing.

Best regards
Chris

Scripts drop-down at the top of CCS, I cannot find "Emu Boot Mode Select" menu, only "No scripts available"

I loaded the led_ex1_blinky example from C2000Ware onto my own board.

But this example can boot when power on without CCS.

Their .cmd file is almost same except CLA part.

led_ex1_blinky does not use CLA function in .cmd file. Is it effect to auto-boot?

BR

Paul

Paul

Yeah, you need to use a target config file with GEL to see the scripts.
What you mentioned doesn't effect boot.

If you monitor the XRS pin, do you see your device reset when booting your app? I still think it is odd you are getting itrap, so either device may be getting reset or some other issue in your code. Double check that something is programmed to 0x80000 (BEGIN) for your app.
Also, for sake of debug, confirm that code_start is keeping watchdog disabled.

Best regards
Chris

Chris,

I changed the main() with led_ex1_blinky.c, leave other code included, but not called. But fail to boot.

Watchdog is disable when app is started calling "SysCtl_disableWatchdog();"

XRS pin is connected with reset circuit.

When I press reset button, CCS is changed as this.