• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 83 subscribers
  • Views 391 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280049: Possible race condition with the EPWM 4-bit event trigger counter loading from ETCNTINIT[SOCxINIT] and incrementing simultaneously when TBCTR equals zero

Patrick Findling
Prodigy 210 points
Part Number: TMS320F280049

My application is using the 4-bit counter in the EPWM1 event trigger sub-module to generate SOCB on every third PWM cycle (ETPS[SOCBPRD] = 3).  The SOCB event occurs when the EPWM1 TBCTR equals zero (ETSEL[SOCBSEL] = 1).  In addition I have an external sync source that resets TBCTR to zero and the event trigger counter to 1 (ETCNTINIT[SOCBINIT] = 1).  My observation is that when the sync pulse occurs, the event trigger counter loads with 1 and then immediately increments to 2.  This implies that the hardware is designed to load the event counter first, and then process any events that should increment the counter.  This operation works for me as long as it is guaranteed to always behave this way.  My concern is that the load from TCNTINIT[SOCBINIT] and the event counter incrementing are actually simultaneous, and therefore due to this race condition my code could randomly fail due to the event counter loading from TCNTINIT[SOCBINIT] in one PWM cycle but not incrementing the event counter to 2 until the next PWM cycle.

  • 0
    TI__Guru 52010 points
    I believe you should see consistent behavior as you described. I can double check to see if we have internal documentation that mentions otherwise.

    Nima Eskandari
  • 0 in reply to Nima Eskandari
    Prodigy 210 points

    Hello Mr. Eskandari,

    Have you had any luck finding internal documentation on this topic?

    Thanks.

  • 0 in reply to Patrick Findling
    TI__Guru 52010 points
    I did not find any internal document that would state otherwise.

    Are you aware of anything like this?
  • 0 in reply to Nima Eskandari
    TI__Guru 52010 points
    I have requested a response from the design team and will get back to you.
  • 0 in reply to Nima Eskandari
    TI__Genius 10845 points

    Hi,

    Please find below the response from design team:

    The observation looks correct only. But the usage of the hardware doesn’t seem proper as the SYNC is being used to load the counter = 0 as well as initialize the SOCBCNT which is also incremented on CNT==0.

    Actually, the user is creating 2 count for each sync, which is not correct.

    However, I believe there is no race condition as the sync is causing the phase load to cnt=0 and will happen in subsequent cycle only.

    Thanks

    Vasudha

  • 0 in reply to Vasudha Bhadoria
    Prodigy 210 points

    Hello,

    I am aware that sync resetting TBCTR to zero results in three simultaneous operations (TBCTR gets set to zero, SOCB event counter gets loaded with one, and SOCB event counter incrementing by one).  Per my original post, I need TI to confirm whether or not the microcontroller hardware is designed to properly support these simultaneous events.

    Please clarify the statements "usage of the hardware doesn’t seem proper as the SYNC is being used to load the counter = 0 as well as initialize the SOCBCNT which is also incremented on CNT==0" and "the user is creating 2 count for each sync, which is not correct".  These statements imply that the microcontroller hardware is NOT designed to support the simultaneous events described in my original post.

    I am not sure about the statement "there is no race condition as the sync is causing the phase load to cnt=0 and will happen in subsequent cycle only".  Is this stating that if sync occurs during cycle N then during cycle N both TBCTR will be reset to zero and the SOCB event counter will be reset to one, and then during cycle N+1 the SOCB event counter will be incremented by one?  Similar to my original post, as long as TI can guarantee that the microcontroller will always behave this way then I can still use this.

    Thanks, Patrick.

  • 0 in reply to Patrick Findling
    TI__Guru 52010 points
    I think the statement is made because It is not common use of the module to both reset the count and increment on the same type of event (CTR=0)