LAUNCHXL-F28379D: how to change sysclk value

Hi Silsio,

The Launchpad comes with a 12MHz crystal.  Normal applications use the internal PLL to produce higher clock rates for SYSCLK (typically 200MHz in the example codes).  You can bypass the PLL and divide the clock to /12 to produce a 1MHz SYSCLK.  To do this, you need to clear SYSPLLCTL1[PLLCLKEN] to 0 and need to assign the value 6 (0x0110 - div by 12) to SYSCLKDIVSEL[PLLSYSCLKDIV].  Make sure also to source the clock from the external crystal.  This will be done through register CLKSRCSEL[OSCCLKSRCSEL] by setting the value to '1'.  You can refer to the system clocking scheme in the "Clocking" chapter of the TRM and registers section for details.

Hope this helps.

Best regards,

Joseph

I have made the changes you have specified:
ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL=1;
ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN=0;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0x0110;

However, im getting an error saying:
C28xx_CPU1: File Loader: Verification failed: Values at address 0x82000@Program do not match Please verify target memory and memory map.
C28xx_CPU1: GEL: File: .... a data verification error occurred, file load failed.

Also, I have cpu1timer in my code:
ConfigCpuTimer(&CpuTimer1, 200,1000);
CpuTimer1Regs.TCR.all = 0x4000;


do i need to change them as well?

The error about verification fail indicates that the code did not program to flash. It should have nothing to do with the code changes you made. Not sure where you use the timer for but this should not cause the program loading error. You would definitely have to change the timer params to match your 1MHz SYSCLK once the program starts loading.

When you compiled and loaded your code, did the flash go through an erase cycle?

No I does not execute. I keeps giving the same error again and again. II tried running other example programs on the same board and it gives the same error. 

EDIT: Now, I have a different set of errors:

C28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU1: Flash Programmer: Warning: The configured device (TMS320F28379D), does not match the detected device (). Flash Programming operations could be affected. Please consider modifying your target configuration file.
C28xx_CPU1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0xc0eb: (Error -1066 @ 0xC0EB) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 8.0.803.0)
C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint
C28xx_CPU1: Error writing the PLL values. (Flash algorithm returned error code). Operation cancelled.
C28xx_CPU1: File Loader: Memory write failed: Unknown error
C28xx_CPU1: GEL: File: ....: Load failed.
C28xx_CPU1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0xc056: (Error -1066 @ 0xC056) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 8.0.803.0)
C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint
C28xx_CPU1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0xc056: (Error -1066 @ 0xC056) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 8.0.803.0)
C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint

You first need to isolate what is causing you not to be able to program the code to the Launchpad.  If you are using CCS to edit, compile, debug and load your code, make sure that on the on-chip flash tool, you need to ensure that erase is done first before programming.

Regards,

Joseph

How to I do that?

Once your target is connected: Go to Tools -> On-chip Flash and make sure to highelight the "Erase and Program" and "Entire Flash" radio buttons as below:

Try this first on several codes to make sure your programming issue is fixed.

Regards,

Joseph

Hi,

I tried executing multiple example codes. I made sure that the setting are correct. But, I have the same issue. It doesnt execute at all. I even ran the Example_28379D_launchpad code and the result is the same.

Also, I tried the same code on another board. The same thing happens to the other boardas well. I worked fine before i dumpedm y code. But after I loaded my code, it stopped working.

UPDATE: solved this issue by turning off the 3 switches on s1 boot on launchpad. It works fine now.

However, when i change the clock values, it gets locked again.

Also, I want to add that the clk frequency reduction is required for sending data over sci data transmission. Even reducing clk frequency for scia would work for me as well.

Soprry, not sure what you meant by "solved this issue by turning off the 3 switches on s1 boot on launchpad. It works fine now. However, when i change the clock values, it gets locked again.". Are you trying a different boot mode through SCI?

Regards,
Joseph

The switch i was talking about is in the blue circle. I don't know why, but once i pulled down those switches and pulled them back up, the errors stopped popping and was able to load examples without issues. I'm not trying boot mode with sci. I just want to send data from SCI at a slower frequency.

I am able to bring sysclk to 120MHz. I used lspclk to bring it down to 8.5Mhz. Can you help me bring it down further?

when i try to change it to:

#ifdef _LAUNCHXL_F28379D

InitSysPll(XTAL_OSC,IMULT_24,FMULT_0,PLLCLK_BY_24);

it is supposed to reduce the sysclk to 10MHz, which is supposed to be attainable. I declared:

#define CPU_RATE   8.333L   // for a 120MHz CPU clock speed  (SYSCLKOUT)

and:

ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 0;

              SciaRegs.SCIHBAUD.all =0x0000;  // 9600 baud @LSPCLK = 10MHz

                                                   //(10 MHz SYSCLK).

              SciaRegs.SCILBAUD.all =0x0082;

However, it doesnt execute when i run the code. When i terminate the code, it starts publishing the data over uart. What might be the cause?

Coluld this be the cause for it?

   

//

   // Set waitstates according to frequency

   //

   //      *CAUTION*

   // Minimum waitstates required for the flash operating at a given CPU rate

   // must be characterized by TI. Refer to the datasheet for the latest

   // information.

   //

   #if CPU_FRQ_200MHZ

   Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3;

   #endif

   #if CPU_FRQ_150MHZ

   Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;

   #endif

   #if CPU_FRQ_120MHZ

   Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2;

   #endif

This code is present in initFLash. How do i change it?

Can anyone help me with this?

Silsio,

Have you looked into the SCI section to see how to reduce the SCI baudrate without reducing the SYSCLK frq. SCI has internal clock divider to achieve required baud rate. Please refer section "19.12 SCI Baud Rate Calculations" in device TRM.

On Flash waitstate, since you are running at lower frq, it should not be issue with waitstate.

Regards,

Vivek Singh

Yes, I looked into it and changed the values accordingly. However, if I try to reduce it below 8.571MHz(120 to 8.75MHz using lspclk), I get more issues. I used:
InitSysPll(XTAL_OSC,IMULT_24,FMULT_0,PLLCLK_BY_2); which gives 120MHz.

hbaud-0x0000;
lbaud-0x006f;

This is for 120MHz and it works without issues. The issues arise when i try to bring cpu frequency below 120MHz(as mentioned in my previous comment).
I just want to decrease CPU frequency to 10 MHz at least. What am i Missing?

Can anyone help me with this? I'm still waiting for this to be solved.

Hi, I'm still waiting for the issue to be resolved.