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Original question:

TMS320F28379D: Resetting CMPA when the HRPWM is configured for duty-cycle control in up-down mode

TMS320F28379D: Additional clarification regarding HRPWM duty cycle range limitation

Pierre Bouchet1
Expert 2575 points
Part Number: TMS320F28379D

Hi,

This a follow-up question to our exchange last year regarding the proper way to achieve 0% or 100% duty cycle when using HRPWM enabled (this is on ePWM Type 4). As stated in the TRM, "the duty cycle must not fall within the restricted range". 

Since there are several distinct features in the ePWM module which can affect the duty cycle by triggering edges, my new question concerns what exactly qualifies as "the duty cycle". 

  1. Obviously using the CMPA/CMPB comparators is one such feature and the documentation clearly says that these register values cannot be within 3 cycles of the PRD or ZRO events.
  2. Conversely  suggested the use of the AQCSFRC feature to achieve 0% or 100% duty cycle, so I assume the falling edge created by AQCSFRC is allowed to fall within 3 cycles of PRD or ZRO events?
  3. What about other events in the Action Qualifier module? Let's say I set up a signal with HRPWM in symmetric duty mode, with pulses centered on PRD (CAU = rising edge / CAD = falling edge). If during operation I reconfigure the module to CAU = rising edge / ZRO = falling edge it means the falling edge will occur at ZRO, in the middle of the forbidden range. Is this allowed or will it cause undefined behavior? The result would be the same as using AQCSFRC with RLDCSF = 0 but the code would be simpler since AQCTLA/AQCTLB are separate registers whereas AQCSFRC is a single register for both outputs.

Thanks and regards,

Pierre

  • 0
    TI__Guru 52020 points

    Okay so 1 is easy and we agree on.

    Now for the rest of the scenarios, here is the general rule.

    The MEP is not gonna place a correct EDGE if you are putting the edge between 0-3 TBCLK cycles from the restricted events. Thats it. If you want your edge to be placed correctly, it has to be after/before 3TBCLK cycles from the restricted range.

    The falling edge/ rising edge from force events don't get HiRES edge placement.

    To get down to 0%, or up to 100% duty, (without hires) you have multiple options. One of them is the one I mentioned in the other posts, others are changing AQTCLA/B events to always be high/low. depends on how you want to program them.

    Pierre, 

    I'm sure I missed to answer a question, so let me know what I missed and I'll answer it. I love the numbered/bulleted questions format. Makes it easier to answer.

    For the restricted range, think of "is my edge that I programmed, going to be withing 3cycles or not?" and do not consider FORCED events or trips.

    Nima

  • 0 in reply to Nima Eskandari
    Expert 2575 points

    Nima,

    So if I make a recap of your answer in terms of which registers to use in my specific case:

    1. The edges generated by AQCTLA[PRD] and AQCTLA[ZRO] get hi-res placement but since they are by definition in the middle of the restricted range they cause undefined behaviour.
    2. The edges generated by AQSFRC[OTSFA] don't get hi-res placement so they can never cause undefined behaviour.

    Is this correct?

    Kind regards,

    Pierre

  • 0 in reply to Pierre Bouchet1
    TI__Guru 52020 points

    That is also my understanding!