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Original question:

TMS320F280049: HRPWM period control jitter in up-count mode

TMS320F28375D: Period jitters on their HRPWM outputs.

Hideaki Nambu
Mastermind 9165 points
Part Number: TMS320F28375D

Hello,

My customer’s F28375D has *period* jitters on their HRPWM outputs.

Could you please advise how to clear the jitter ?

 

Jittter description:

My customer found several falling edges.

- The total # of high time variation is not clear. We are sorry.

- The input clock for EPWM is 10nsec.

 

 

The TRM SPRUHM8i has a description in “15.14.1.5.4 High Resolution Period”.

On the p.1967, There is a note:

>>>>> 

NOTE: When high-resolution period mode is enabled, an EPWMxSYNC pulse will introduce +/- 1 - 2

cycle jitter to the PWM (+/- 1 cycle in up-count mode and +/- 2 cycle in up-down count

mode). For this reason, TBCTL[SYNCOSEL] should not be set to 1 (CTR = 0 is

EPWMxSYNCO source) or 2 (CTR = CMPB is EPWMxSYNCO source). Otherwise, the jitter

will occur on every PWM cycle with the synchronization pulse.

When TBCTL[SYNCOSEL] = 0 (EPWMxSYNCI is EPWMxSYNCO source), a software

synchronization pulse should be issued only once during high-resolution period initialization.

If a software sync pulse is applied while the PWM is running, the jitter will appear on the

PWM output at the time of the sync pulse.

<<<<< 

 

From the note, we understand that the PWM outputs have period jitters under some condition.

 

Then, could you please advise how to remove the jitters in the following usage ?:

  • The F28378D is required to output a couple of EPWM modules to output complemental PWM outputs.
    •  A single module output EPWMxA and EPWMxB signals.
    • Two modules work in synchronous.
  • The period is in high-resolution. The value is more than ten or a hundred.
  • The count mode is up-down.
  • The PWMs toggles at the CTR=zero in the module.

 

 

We are aware of the PWM connection. The TRM has a figure on p.1876.

We can use three or more PWM modules if we need to use EPWM1 as oscillator only, and use EPWM2 and -3 to output PWMs.

 

 

 

  • 0
    TI__Guru 52020 points

    Can you clarify what the ePWM configuration is exactly,

    The Action qualifiers,

    The HRMODE

    and so on?

    Nima

  • 0 in reply to Nima Eskandari
    Mastermind 9165 points

    Nima,

    Thank you for your response.

     

    /cfs-file/__key/communityserver-discussions-components-files/171/191127_5F00_files.zip

     

    My customer provided their test code files. Please check.

    • Their goal is to remove jitters from ePWM[1,4] Period and Duty.
    • The code operates ePWM[1,4] and ePWM6. The original intended modules were ePWM[1,4]. The codes for ePWM6 was added for debug. ePWM6 output toggles at CTR=zero to evaluate the period. The oscilloscope plot was taken from the ePWM6. Now our interim goal would be to remove period jitters from ePWM6.

     

     

     

    Files:

     

    [Epwm.c]

    • EpwmInit() initializes most of ePWM registers.

     

    [EpwmCla.cla]

    • This file was shared to show that the CLA configures TBPRD and TBPRDHR in InitializeEpwm().
    • Cla1TaskTEST() is triggered by ePWM1, but the function doesn't change the periods. Therefore, I think the function is not harmful this time.

  • 0 in reply to Hideaki Nambu
    TI__Guru 52020 points

    I will look over the code and get back to you!

  • 0 in reply to Nima Eskandari
    TI__Guru 52020 points

    Why do you have PHSEN for ePWM1? What is the source for the synchronization? It is a possibility that a continuous sync source is causing the jitter?

  • 0 in reply to Nima Eskandari
    Mastermind 9165 points

    Nima,

    Thank you for your response.

    I will check the code again.

  • 0 in reply to Hideaki Nambu
    Mastermind 9165 points

    Nima,

    Let me share the response from my customer:

     

     

    >> Why do you have PHSEN for ePWM1?

    Your comment would came from: [Epwm.c: Ln24] EPwm1Regs.TBCTL.bit.PHSEN = 1;

    The line came from the TRM(spruhm8i.pdf), p1967, “15.14.1.5.4.1 High-Resolution Period Configuration”, step-6:

    6. For TBPHS:TBPHSHR synchronization with high-resolution period, set both

    HRPCTL[TBPSHRLOADE] = 1 and TBCTL[PHSEN] = 1. In up-down count mode these bits must be

    set to 1 regardless of the contents of TBPHSHR.

     

    The ePWM1 is used as up-down count mode, the step-6 is implemented to their code.

     

     

     

    >> What is the source for the synchronization?

    None of intended source for ePWM1.

     

     

     

    >> It is a possibility that a continuous sync source is causing the jitter?

    They will try again with TBCTL[PHSEN]=0. Please wait for some days.

     

  • 0 in reply to Hideaki Nambu
    Mastermind 9165 points

    Nima,

    Thank you very much for your responses.

    My customer tried TBCTL[PHSEN]=0, but their jitter was not cleared.

     

    By the way, can I ask one more question?

    I found the following thread. The second post states that user should avoid the action by the bitfield ZRO. Do you agree with this ?:

    http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/544567

     

    Let me correct that toggling at EPWM6A at zero is not for test only, but my customer would like to do the same thing in their final application.

     

  • 0 in reply to Hideaki Nambu
    Mastermind 9165 points

    Nima,

    Please forgive my reminder.

     

    In the following thread, the second post states that user should avoid the action by the bitfield ZRO. Do you agree with this ?:

    http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/544567

    Please tell me if a new thread is convenient for you.

     

  • 0 in reply to Hideaki Nambu
    TI__Guru 52020 points

    The issue is that there seem to be a continous sync occuring. You want your HRPWM PWM waveform to be centered around PRD and not get a continuous sync on ZERO. The code snippet from the TRM is showing how you sync up other PWMs hence the PHSEN, not the MASTER PWM. 

  • 0 in reply to Nima Eskandari
    Mastermind 9165 points

    Nima,

    Thank you for your response.

    I could not catch from your post, so please forgive my confirmation.

    You mean that the HRPWM actions at AQCTLA[ZRO] should be avoided, otherwise jitters may be occurred.

    Is it correct ?

    My customer would like to make sure this point, therefore I would like you to clarify it. Please. 

    Thank you for your cooperation.

  • 0 in reply to Hideaki Nambu
    TI__Guru 52020 points

    No I mean, make your ePWM signal for HR application be centered at PRD. You can still use CTR=ZERO but try to  make CTR=ZERO to set ePWM output LOW, CMPA set the ePWM output HIGH and then at CMPA for Counter Down action set the ePWM output LOW again.

  • 0 in reply to Nima Eskandari
    Mastermind 9165 points

    Nima,

    I appreciate your input. I understood that, if the ePWM output is already low, CTR=ZERO can set ePWM output LOW again. In this case the PWM output doesn't change at CTR=ZERO and no jitters.