TMS320F28069: two TMS320F28069 PWM for synchronization

Phenomenon:

Two independent DSPs (TMS320F28069PAG) generate PWMs with fixed frequency (20kHz) and fixed duty cycle (50%) respectively. Test the PWM waveforms of the two DSPs with an oscilloscope. Set one of the PWM rising edges as the trigger). At this time, the two DSPs output PWM with the same frequency and the same duty cycle, but there is relative movement between the PWM. The frequency of the two DSP crystals is 20MHz, and the internal clock is 90MHz. All circuits remain the same.

 The frequency of the two DSP crystals is 20MHz, and the internal clock is 90MHz. All circuits remain the same.

 The EPWM configuration is as follows:

  EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;        

  EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;

  EPwm1Regs.CMPA.half.CMPA = EPWM1_TIMER_TBPRD;

  EPwm1Regs.CMPA.half.CMPAHR = 0;

  EPwm1Regs.CMPB = EPWM1_TIMER_TBPRD;

  EPwm1Regs.TBPHS.all = 0;

  EPwm1Regs.TBCTR = 0;

  EPwm1Regs.TBPHS.half.TBPHS = 0;

  EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

  EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;

  EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;

  EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;

  EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

  EPwm1Regs.TBCTL.bit.FREE_SOFT = 3;

  EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;

  EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;

  EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

  EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

  EPwm1Regs.AQCTLA.bit.ZRO= AQ_SET;

  EPwm1Regs.AQCTLA.bit.PRD= AQ_CLEAR;