TMS320F28374D: issues in Breakpoints on CPU2

Carlo,

Let me see if I understand correctly.

On CPU2 there are 2 interrupts.  Placing a breakpoint inside one halts correctly.  Placing a breakpoint inside the second one does not halt.  On CPU1 in both cases it halts.

Can you confirm that the second interrupt (where the breakpoint does not halt) is actually being serviced?  I.e. if you place a little while(1) loop in there and then halt is it stuck in the loop.  i.e. is this an issue where the breakpoint is not being set properly by CCS or is this a case where the interrupt does not happen.

Another thing to check if the same code is being used on both cores is to make sure that the breakpoint is being set on the correct context.  If debugging a multicore device I like to setup the breakpoint view to group breakpoints by "debug context".  This can be done by clicking on the 3 virtical dots in the breakpoints view and selecting Group By -> debug context.

Regards,

John

Hi Carlo,

Colombo Carlo said:

I do not believe it is related to the action of code, because, it does enter sometimes when used CCS10, while does not enter using CCS7.

You mentioned that it sometimes works with CCS10. I assume that this means that it will still periodically fail. Correct? And that it always fails with CCS7?

If the customer could provide a small, reproducible test case, that would be very helpful. The example should be generic and basic enough that it can work on a variety of targets (I have a 28377d controlcard that I can use).

Thanks

ki

Hi JohnS,

I run LED blink code at the beginning of the interrupt (which does not halt on the setup of the breakpoint) and it seems that the interrupt is not being served in the debug mode. So, the LED did NOT blink 3 times out of 5 trials. Let me know for other test cases I can run for further debugging of the problem.

Thank you. 

Well one thing that could cause that when using the debugger is a halt.  For example if there is a printf statement in your code that will result in a temporary halt.  The core will halt when the statement is reached, data is transfered to the host and then the core is run again.  If your interrupt was triggered during the time the core was halted then it would not be serviced. 

On F28x it is possible to enable something called real-time mode and to service critical interrupts even when halted.

In CCS you can enable real-time mode here in the project settings:

You can also turn this on in an active debug session by clicking the button on the left below:

There is some more information on this at the links below:

https://e2e.ti.com/support/microcontrollers/c2000/f/c2000-microcontrollers-forum/22881/f28x-real-time-mode---interrupts

https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_debug-main.html#real-time-mode

Regards,

John

Hi John, 

I executed the steps suggested by you as well as the links,

One of the suggestions I followed is:   I flashed the code on both the cores, then I followed as 1) Debug configurations-->program-->load symbols only, 2) target-->Autorun and launch options--> enable realtime mode (critical interrupts...),  but then it fails to load the program in all cases and shows the error as in the picture attached.

Also, I do not have any printf statements in the code. 

BR, 

Vidhi  

Vidhi,

Try just loading the program normally and then turning on Real-time mode after the load is done with the button on the toolbar.

Any chance that you could provide us with a test case to reproduce this?  It can be sent via private message if you don't want to post in the public forum.  Ki has a F28377D and I have a F28379D.

Regards,

John

Hi Vidhi,

Colombo Carlo said:

one breakpoint inside one interrupt, and another breakpoint inside another interrupt, In CPU2. The first breakpoint pauses the program and so ok, but the second breakpoint is not pausing the program

One item to keep in mind when you are using multiple interrupts: if one interrupt ISR is executing, no other interrupts will execute during that time. The only way for one ISR to interrupt another ISR is to use nested interrupts. See the following thread on nested interrupts for more information: https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html

Make sure that the second interrupt is happening after the first interrupt is completely finished executing.

Regards,

Vince

HI John , 
I shared  offline  code   : please let me know  if you need anything else 

thank you 

BR
Carlo

Thanks.  We will give this a try.

Regards,

John

Continuing to work this one offline