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TMS320F28377D: Any suggestions to implement the ADC function?

Part Number: TMS320F28377D

Hi,

I have been troubled for how to implement the ADC funtion for few days and I hope for some suggestions. The function I need is like the picture above.

EPWM1 and EPWM2 are two pwm, the period is 100us, and the duty cycle is 20%. I need to start sampling at the point at CMPA event, and then I need to sample as much as possible between the CMPA and CMPB event, for both EPWM1 and EPWM2. And EPWM2's CMPA event is later than EPWM1's CMPB event. Finally I need to separate the ADC results according to whether they are sampled in EPWM1's interval or in EPWM2's interval.

Here are my questions:

(1) Which trigger source should I use to trigger the ADC? If I choose 16 bit resolution, then the total time for S+H and conversion will be about 1us according to the manual, and I want to sample as much as possible. However, if I use software trigger in CMPA's interrupt to force the first sample,  and then use the continous sample method( ADCINT1 and ADCINT2 as trigger source), the problem is I can't control when to stop the ADC, but I need to stop after EPWM1's CMPB event (that's because samples after that time are invalid) , and restart ADC at EPWM2's CMPA's event.

(2)   If I can stop ADC at EPWM1's CMPB event, and restart ADC at EPWM2's CMPA event, then the separation seems to be relatively easy. If not, any suggestions on how to separate the results according to the time they are sampled?

Thank you for your time and hope for reply.

Jack

  • Hi Jack,

    Easiest method would be to:

    • Set ePWM1 CMPA triggers for ADC-A SOC0 to SOC15, all set to the same channel
    • Set ePWM2 CMPA triggers for ADC-B SOC0 to SOC15, all set to the same channel
    • Set the S+H duration (controlled by ACQPS) for all samples such that the total conversion time is 20us / 16 
    • Note: if you need all the samples from the same input channel, CH14 and CH15 are mapped to all ADCs

    You can probably squeeze a few more samples in if you use the self-triggering method + DMA.  You only need an ISR to stop the process, not start it, but it still think it ends up being much more complicated:

    • ePWM1 CMPA triggers ADC-A SOC0
    • SOC0 triggers ADCINT1 flag
    • ADCINT1 flag (re)triggers SOC0
    • ADCINT1 flag also triggers DMA to go move ADCRESULT0 to a buffer in RAM
    • (for second pulse, use same method as above, but use ePWM2 trigger, a different SOC,  and a different ADCINT)
    • There is no way in HW to stop the self-triggering, so you need to take an ISR to go in and stop the process and do some clean-up.  
  • Hi Devin,

    Thanks for your reply. I have got some inspiration from it. I apologize for my negligence of explaining my situation. In my case, I need to do these for six channels, like the picture above. I am mapping channel 1 and 2 to module A, and 3 and 4 to module B, ... and so on. EPWM1 and EPWM2 are the common trigger signal for all six channels.

    Here are my questions:

    (1) I know there will be delay due to SOC's priority in the same ADC module. Does that mean it is impossible to sample channel 1 and 2 at the same time in my allocation?

    (2) Due to there are two channels to sample in one module, the easiest way you adviced seems hard to work. I can only assign up to 8 SOCs to one channel, and there will be delay between channel's samples. Could you please give me some other suggestions on how to implement the function ?

    (3)   In the other way you mentioned, take an ISR to go in and stop the self-trigger process, I want to know which ISR you are refering to ?ther EOC interrupt?  

    Thanks a lot for your time and hope for your reply.

    Jack

  • Hi Jack,

    (1) Channels 1+3+5 will be sampled at the same time, then 2+4+6 together.  If you include ADC-D, then you can get 4 samples simultaneously.  

    If you are going to take multiple samples and average them, you can use the following method to get averaged samples with the same center time:

    ch1 > ch2 > ch1

    or

    ch1 > ch2 > ch2 > ch1

    or

    ch1 > ch2 > ch1 > ch2 > ch1

    etc. 

    (2)

    You can sequence the channels however you want in method 1, so you can alternate between ch1 and ch2 or use a sequencing scheme similar to the ones described above.  

    (3)

    The ISR to stop the process would need to come from CMPB or from the DMA reaching a transfer count; the ADC doesn't have any mechanism to count the number of self-triggered samples.