TMS570LS3137: Lock step core configuration

Hello M.Sreenivasan,

sreenivasan m said:

1. Do we have access to lock step core?

From a debug perspective, the lockstep cores appear as a single core. The core designated as the diagnostic core, is not accessible by SW or debug. The only indication of a synchronization error would be the CCMR4 module.

sreenivasan m said:

2. If so, any special conditions/care to be taken?

See note above.

sreenivasan m said:

3. Do we have an application note mentioning the details on this?

Device startup considerations are discussed in SPNA106

Also worth noting, the startup code provided by Halcogen fulfills all the requirements of core synchronization so use of Halcogen generated code as a reference will also serve as a guide to insure compliance to the necessary procedures.

The CCM has self-test mode will will simulate a lockstep error which is how most customers are performing a test of error path or error response mechanism.

If you wanted to create a lockstep error, you could enable the CCM at boot time without performing the synchronization. However, this will not be 100% because the content of the two cores is not guaranteed so it is possible that they could reset to the same content ;but, considering there are 15 registers each with 32 bits the likely hood of the cores being randomly synchronized is very, very remote.

The key for this approach latter approach where you skip the synchronization is how you react to it. Most likely, since it is boot time, the nERROR monitor external to the device would not be in an active state (depends on you implementation and how you monitor the nERROR signal) so it will only result in a Group 2 channel 2 ESM error which generates an NMI where you would have to be able to know the context of the injected error so you could differentiate between the diagnostic check and a real event. If it is the injected fault you would check to insure the correct ESM flag is set and the nERROR pin is asserted. Once it is confirmed that the correct action has occurred, clear the ESM flag and reset the nERROR pin. Once the error condition is cleared, disable the CCM, synchronize the cores then re-enable the CCM and continue with boot up.