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  • TI Thinks Resolved

RM48L940: Clock Monitor Test

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Replies: 7

Views: 262

Part Number: RM48L940

When I run  the clock monitor test, the Clock Fail status register is never set so my test waits infinite at the while((systemREG1->GBLSTAT & 0x1U) == 0U). The PLL Slip test works fine. What can I check to determine and resolve what is going on?

    /* Enable clock monitor range detection circuitry */
    systemREG1->CLKTEST |= 0x03000000U;

    /* Backup register GHVSRC */
    ghvsrc_bk = systemREG1->GHVSRC;

    /* Switch all clock domains to HF LPO */
    systemREG1->GHVSRC = 0x05050005U;

    /* Disable oscillator to cause a oscillator fail */
    systemREG1->CSDISSET = 0x1U;

    /* Wait till oscillator fail flag is set */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while((systemREG1->GBLSTAT & 0x1U) == 0U)
    {
    } /* Wait */

    if((esmREG->SR1[0U] & 0x800U) != 0x800U)
    {
        selftestFailNotification(CHECKCLOCKMONITOR_FAIL1);
    }

  • I tried switching VCLKASRC and RCLKSRC as described in this post e2e.ti.com/.../666751

    Like that poster, it didn't help. The test is stuck waiting for GBLSTAT . Anythings else I can check?
  • In reply to Guy Tadi:

    I came across two additional posts all reporting what I'm seeing now with no clear resolution. That is GBLSTAT doesn't set to "1" in the clock monitoring test. If this test doesn't work then it means a late hardware change to externally monitor the clock. I'd like to avoid such a change if possible so let me know if I can get this work.

    e2e.ti.com/.../424882

    e2e.ti.com/.../350726
  • Hello,

    Please check if the CPU is in privileged mode.
    As per the TRM, to write to the CSDISSET register is allowed in privilege mode only.

    Thanks and Regards,
    Akshay
  • In reply to Akshay Manikantan:

     CPU is Supervisor mode b10011. After CSDISSET = 1, this is the content of clock registers:

  • In reply to Guy Tadi:

    Hello,

    The PLLs need to both be disabled as well. Keeping them ON prevents the main oscillator from getting disabled. In fact you can disable all clock sources other than the LPO (sources 4 and 5). CSDISSET = 0xCF.
  • In reply to Guy Tadi:

    Hello Guy,

    Intentionally disabling the oscillator via the Clock Source Disable register also disables the oscillator monitoring, hence no fault is detected. Another way to generate an oscillator fault would be to disable the HF LPO, but this would cause the device to hang as the HF LPO is also the clock source that the system switches all clock domains driven by the main oscillator.

    We have another feature that can be used in this case. A device terminal, GIOB[2] in case of RM48x, can be used to provide a "limp clock", which is used as reference clock for oscillator monitoring. Assuming this terminal does not carry a clock signal in your application, you can trigger an oscillator fault by enabling use of the alternate limp clock. This is done by setting bit 26 of the CLKTEST register.

    Make sure you switch all clock domains over to the HF LPO before you cause an oscillator fault using this method.

    /* Switch all clock domains to HF LPO */
    systemREG1->GHVSRC = 0x05050005U;

    /* Switch over to unavailable alternate limp clock to cause osc fail */
    systemREG1->CLKTEST |= 0x04000000;

    /* Wait till oscillator fail flag is set */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while((systemREG1->GBLSTAT & 0x1U) == 0U)
    {
    } /* Wait */

    Once the oscillator fault is detected, you do need to perform the recovery procedure as described in the reference manual.

    Regards,
    Sunil

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