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Part Number: RM48L940
When I run the clock monitor test, the Clock Fail status register is never set so my test waits infinite at the while((systemREG1->GBLSTAT & 0x1U) == 0U). The PLL Slip test works fine. What can I check to determine and resolve what is going on?
/* Enable clock monitor range detection circuitry */
systemREG1->CLKTEST |= 0x03000000U;
/* Backup register GHVSRC */
ghvsrc_bk = systemREG1->GHVSRC;
/* Switch all clock domains to HF LPO */
systemREG1->GHVSRC = 0x05050005U;
/* Disable oscillator to cause a oscillator fail */
systemREG1->CSDISSET = 0x1U;
/* Wait till oscillator fail flag is set */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while((systemREG1->GBLSTAT & 0x1U) == 0U)
} /* Wait */
if((esmREG->SR1[0U] & 0x800U) != 0x800U)
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In reply to Guy Tadi:
In reply to Akshay Manikantan:
CPU is Supervisor mode b10011. After CSDISSET = 1, this is the content of clock registers:
In reply to Sunil Oak:
Thanks Sunil. I tried that, but GLBSTAT is still not set
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