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Original question:

RM48L530: RAM ECC Testing - RAMOCCUR not incrementing

TMS570LS0432: SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &failInfoTCMRAM); FAILED

whong zhao
Genius 4080 points
Part Number: TMS570LS0432

Hello 

Team

When my program run the SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &failInfoTCMRAM);make the  _excpt_vec_udef_instr()

And  I find the  SL_SelfTest_SRAM function.which make the problem

  • 0
    Genius 4080 points

    Hello

    eccB1 = &sramEccTestBuff[2];
    /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
    eccB1 = eccB1 + (0x00400000u/sizeof(uint64));

    eccB2 = &sramEccTestBuff[3];
    /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
    eccB2 = eccB2 + (0x00400000u/sizeof(uint64));

    /* Enable Writes to ECC RAM */
    /*SAFETYMCUSW 9 S MR: 12.2 <APPROVED> Comment_10*/
    /*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> Comment_5*/
    BIT_SET(sl_tcram1REG->RAMCTRL, TCRAM_RAMCTRL_ECCWREN);

    /*SAFETYMCUSW 9 S MR: 12.2 <APPROVED> Comment_10*/
    /*SAFETYMCUSW 134 S MR: 12.2 <APPROVED> Comment_5*/
    BIT_SET(sl_tcram2REG->RAMCTRL, TCRAM_RAMCTRL_ECCWREN);

    /* cause a 2-bit ECC error */
    /* Flip 2 bits, this flip in ECC works as 2 bit error when the data part used for ECC is zero*/
    /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> Comment_7*/
    *eccB1 ^= TCRAM_SYN_2BIT_DATA_ECC;  

    *eccB1 ^= TCRAM_SYN_2BIT_DATA_ECC;   It seems there is a problem with this sentence

  • 0 in reply to whong zhao
    TI__Guru**** 190296 points

    Hell Whong,

    The data abort is expected.

    *eccB1 ^= TCRAM_SYN_2BIT_DATA_ECC;   --> is to flip the bits of ECC value (at 0x08401950) to generate uncorrected ECC error when read data from 0x08001950.

    The MCU RAM is protected by ECC allowing the CPU to correct any single-bit errors and detect double-bit errors within a 64-bit value. The error correction codes (ECC) are stored in the RAM memory space as well. The address on which a 1-bit error is detected or a 2-bit error is detected are stored in SERRADDR and UERRADDR registers.

    In my test, the data is located at 0x08001950, and the ECC location of this data is at 0x08401950.

  • 0 in reply to QJ Wang
    Genius 4080 points

    Hello 

    QJ

    Now what is my current problem and how to solve it.

    Do I need to do any tests?

  • 0 in reply to whong zhao
    Genius 4080 points

    /**
    * @file sl_selftest.c
    * @version 2.4.0
    * @brief File contains the Self Test APIs

    Do you use this library?

  • 0 in reply to QJ Wang
    Genius 4080 points

    Hello

    when run 278 line picture ,next step run  ,make  _excpt_vec_udef_instr()

  • 0 in reply to whong zhao
    TI__Guru**** 190296 points

    Hi Whong,

    This function is declared in the library but not defined there. You need to define this function to process the error.

    When you run the selftest, you inject a fault and expect an error. After an abort occurs, you need to clear the error flag (peripheral registers and ESM registers), and restore the nERROR pin state. This should be done in this exception handler.

    Attached is an example:

    7838.dabort.asm

  • 0 in reply to QJ Wang
    Genius 4080 points

    Hello 

    Thank you

    Wasting your time.

    1.which function is declared in the library but not defined there??? library 2.4.0/demo/common/soure/exception_handlers

    2.3051.dabort.asmWhere can I find the link? Is there such a situation? not defined in library

    3.exception_handlers.c _excpt_vec_abort_data() is not complete,Is something missing？

  • 0 in reply to whong zhao
    Genius 4080 points

    Thank you

    The problem is solved