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TMS570LC4357: TMS570LC4357 STC Self Test Query

Kalyan Vagvala61
Expert 1075 points
Part Number: TMS570LC4357

Hello Team,

I have an issue in clearing the status of STC registers after the test. Below are the steps i am doing:

1. Perform STC self test and keep the controller in idle mode.

2. Controller resets and could verify that it is due to CPU reset by reading SYSESR register.

3. After verifying that reset is due to STC self test below steps are not working. This resulting in not able to perform CPU self test.

Even i am writing 0x5 to STCSCSCR register, i couldn't see the 0x5 in STCSCSCR register.

Even i am writing 0x3 to STCGSTAT register, i couldn't see respective bits getting cleared.

Can you please help me in understanding what could cause this issue?

Thanks,

Kalyan

  • 0
    TI__Guru**** 190426 points

    Hello,

    The flags should be cleared by writing 1 to the flag bits in STCFSTAT and STCGSTAT register. Writing 0x5 is to SELF_CHECK_KEY in STCSCSCR is to disable the self check, this bit field can only be written in privilege mode. 

  • 0 in reply to QJ Wang
    Expert 1075 points

    Hi Wang,

    Thanks for your quick response. 

    My code has instructions to Write 0x5 is to SELF_CHECK_KEY in STCSCSCR and 0x3 to STCGSTAT registers, but i could see STCSCSCR  and STCGSTAT  registers status bits are not getting cleared.

    As STCSCSCR  and STCGSTAT registers can be written only in privilege mode, i tried clearing these flags after changing ARM mode to Supervisory mode (CPS #19). but not successful.

    Would like to get your inputs on this.

    Thanks,

    Kalyan

  • 0 in reply to Kalyan Vagvala61
    TI__Guru**** 190426 points

    Hello Kalyan,

    I tried couple times, there is no problem to write 0x5 to STCSCSCR[4:0] (0x1A-->0x05), and to clear STCGSTAT[1:0] (0x3 --> 0x0).

  • 0 in reply to QJ Wang
    Expert 1075 points

    Hi Wang,

    Thanks for your response. The issue got resolved when i changed the CLKDIV0 field of STCCLKDIV register from 1 to Zero.

    As per my understanding the clock speed should affect only the current dissipation and shouldn't result in test. Can you please help me understanding what the reason could be?

    Thanks,

    Kalyan

  • 0 in reply to Kalyan Vagvala61
    TI__Guru**** 190426 points

    Hello Kalyan,

    The maximum clock rate for the CPU self-test is 110 MHz. The STCCLK is divided down from the GCLK clock. This divider is configured by the STCCLKDIV register. The divider in STCCLKDIV takes effect only when the value in the CLKDIV field of the STCLKDIV register (SYS2 module) is zero.

    My understanding is that the clock divider should not affect the writing of the register.