• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 79 subscribers
  • Views 335 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430FR2032: MSP430FR2032 control board

Jonathan Navor
Genius 9385 points
Part Number: MSP430FR2032

Hi Team,

Good day! This is our customer concern below and I'm posting it on their behalf.

My immediate problem is that on my new MSP430FR2032 hand control board,

SMCLK appears to be running about 5% fast, instead of 1.00 MHz.

This is evidenced by scoping the bit times on both

the UCA0 as uart at 9600 (99 usec instead of 104usec), and

the UCB0 as spi, with shorter than expected bit time.

And so maybe the FLL is not locked?

Disabling the 32.768 kHz crystal does not help,

gives same discrepancy.

 

I’ve searched the examples in Resource Explorer.

Tried a lot of things, but instead I have to empirically offset

the prescaler from 104 to 110 for the connected uart LCD to work.

 

       UCA0CTLW0 |= UCSWRST;//uart held in RESET for config

        UCA0CTLW0 |= UCSSEL__SMCLK;//SMCLK=1 MHz

        UCA0BRW = 110;//1e6/9600 = 104.17 

//should be 104, SMCLK is running fast    

//       UCA0BRW = 6;//=1000000/16/9600 if oversampling used

//       UCA0MCTLW = 0xAA00 | UCOS16 | UCBRF_8;

        P1SEL0 |= BIT0 | BIT1;//P1.1=RXD, P1.0=TXD

Best regards,

Jonathan

  • 0
    Guru 91230 points

    I'm not familiar with this board (or its firmware). Is it possible to post your clock initialization code? ~5% would be not-inconsistent with FLLN being off-by-1.

    MCLK is pinned-out directly on P1.4, if that's useful. [Ref data sheet (SLASE45E) Table 6-14]

  • 0 in reply to Bruce McKenney47378
    TI__Guru 56685 points

    Hello Jonathan,

    I'm not familiar with this hardware as we don't have any EVM that directly uses this MSP430. that being said, if you are having trouble with clocking, in particular DCO + FLL locking, please see the following application note that explains how to do this properly on the MSP430FR2xxx and MSP430FR4xxx devices. 

    MSP430FR2xx/FR4xx DCO+FLL Applications Guide

  • 0 in reply to Jace H
    TI__Genius 9385 points

    Hi Team,

    Here is the customer response below:

    Thanks Bruce and Jace.

    We are using the FR2032 device for our team here because it is available in stock, most others are sold out. 

    With regard to your note on the EVM, we patch the 4 programming jumpers from our FR2355 or FR2476 EVMs, and use these simple tools for development debug and program in our shop.  

    As inquired, below is the setup code for the spi, in this case.

     

        UCB0CTLW0 = UCSWRST;//Hold UCB1 in reset  SPI   

        UCB0CTLW0 |= UCMODE_0 + UCSSEL__SMCLK + UCCKPH + UCMST + UCMSB + UCSYNC;//SPI mode 

        UCB0BRW = 10;//

        P5SEL0|=BIT1|BIT3|BIT2;//P5.1=ucb1 SPI clk P5.3=ucb1SOMI P5.2=ucb1SIMO

    The baud rate word of 10, and SMCLK of 1.00 MHz would seem to yield a 10 usec bit period.

    But when we looked at the spi clock with the scope, its period is about 9.5 usec, instead of 10 usec.

     

    Slau445i User Guide para 3.2 states

    After PUC, DCO locked by FLL operation with XT1CLK is selected by default. The FLL stabilizes MCLKand SMCLK to 1 MHz and fDCOCLKDIV = 1 MHz

     

    But after reading the app note link on the clock system that you referenced, we looked at table 3-5. CSCTL1 Register Description of User Guide slau445i.

    It shows CSCTL1 has a 3-bit field, 'DCORSEL' has a default [PUC] value 001 which corresponds to 2 MHz.

     

    Some here thought this might be a conflict, but normally default values play together. We do appreciate your help, and will continue to keep you apprised of our findings.

    Best Regards

    Jonathan

  • +1 in reply to Jonathan Navor
    TI__Guru 56685 points

    Hello Jonathan,

    To get a more accurate 1MHz clock, it is recommended to go through the procedure outlined in the app note above to get better FLL locking. We only trim for accuracy in factory for 16MHz and 24 MHz (procedure to lock these in app note). Look at section 3.2 in the app note to lock to a different frequency. Locking to 1MHz could save you current/overall power consumption if your application is not to extensive.

    Personally, I would lock it to 16MHz and divide down for SPI and UART. Then spend most of my time in a low power state. 

  • 0 in reply to Jace H
    TI__Genius 9385 points

    Hi Jace,

    Our customer had run at 16 MHz, using some help from Resource Explorer example from MSP430FR413x_CS_03.c. This is considered solved. 

    However, would you help us also on our customer's new related question. Or should we create new post for this?

    We have a new question on the new IDE version of CCS Cloud. 

    As per customer:

    On the old Legacy version, I could highlight a constant or register, right click for a dropdown list, and select “Go to definition”, and it would pull up the cmd file with the selected definition highlighted.

    This was very useful for validating syntax or interpreting the selection.

    But with the new version, the right-click drop down list has greyed out the “Go to definition”, and it is not selectable.

     Can you tell me if this function is available and any tips for usage?

    Best regards,

    Jonathan

  • 0 in reply to Jonathan Navor
    TI__Guru 56685 points

    Hey Jonathan,

    Yes, please make a new thread with this additional subject as another group would handle this type of question. 

**Attention** This is a public forum