MSP430FR5739 RTC Configuration

Hello Ralf, did you get your RTC code running?

For the MSP-EXP430FR5739 dev board, my RTC is running just fine. I have it set to interrupt at 1sec intervals. You will need to make sure that XT1 is enabled as well. You can replace RTCRDYIE with RTCTEVIE to use the event interrupt instead of the read ready interrupt. My code is below, along with the ISR:

// rtc initialization
void RTC_init(void)

{

RTCCTL01 |= RTCBCD + RTCHOLD + RTCRDYIE; // bcd mode; hold rtc for setting; enable rtc ready interrupt; 1sec

RTCSEC = 0x00;

RTCMIN = 0x30;

RTCHOUR = 0x04;

RTCCTL01 &= ~RTCHOLD; // release rtchold, begin count

}

// clock init
void CS_init(void)

{

PJSEL0 |= BIT4 + BIT5; // XT1

CSCTL0_H = 0xA5;                          // Unlock register

CSCTL1 |= DCOFSEL0 + DCOFSEL1;            // Set max. DCO setting

CSCTL2 = SELA_0 + SELS_3 + SELM_3;        // set ACLK = XT1; MCLK = DCO

CSCTL3 = DIVA_0 + DIVS_0 + DIVM_0;        // set all dividers 

CSCTL4 |= XT1DRIVE_0; 

CSCTL4 &= ~XT1OFF;

do

{

CSCTL5 &= ~XT1OFFG;               // Clear XT1 fault flag

SFRIFG1 &= ~OFIFG; 

}while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

CSCTL0_H = 0x01;                          // Lock Register

}

// RTC_b isr

#pragma vector=RTC_VECTOR

Hello Greg and others,

thanks for this answer and the sample code.

I do have a similar problem with getting the rtc-timer to run on the MSP430FR5739 experimenters board. I first soldered the 32kHz oscillator with two capacitors 12.5nF each onto the board.

The µC should work in sleep-mode 3/4, later in LPMx5 and wakeup from TimerA0-Interrupt sourced from the RTC. I do not want to use the RTC-Interrupts, is it possible to use the XT1-clk without interrupts ?.

Following code-lines were used to initialize the RTC-Timer

First: Select the PJSEL0.4 and PJSEL1.4 Bits to use a crystal-oscillator (according to datasheet if correctly understood).

PJSEL0 |= BIT4;                // Enable Crystal on XIN-Pin, Bit5 does not matter XT1BYPASS = 0;
PJSEL1 &= ~BIT4;

Then in the init routine set the clock-source for ACLK to XT1.

CSCTL2 = SELA_0 ...

'Complete' Init Function

void system_init()
{
    PJSEL0 |= BIT4;                // Enable Crystal on XIN-Pin
    PJSEL1 &= ~BIT4;
                                                         
    // Startup clock system in max. DCO setting ~8MHz
  
    CSCTL0_H = 0xA5;                                                 // Password protection register, writing 0xA5 enables write access to CS-Registers
    CSCTL1 = DCOFSEL0 + DCOFSEL1;                // CLK frequency selection register      Set DCO - clk to 8 MHz
    CSCTL2 = SELA_0 + SELS_3 + SELM_3;         // CLK assignment register, ACLK <= XT1; MCLK,SMCLK <= DCO, VLO = int. low-power osc., dco = digit. ctrl. clk
    CSCTL3 = DIVA_0 + DIVS_0 + DIVM_0;             // CLK division register, all clocks full speed, no division
    CSCTL4 = 0;                                                            // Configure XT_Clk   
    //CSCTL4 &= ~(XTS + XT1BYPASS + XT1OFF);      // Configure XT_Clk  alternativly
       
    CSCTL0_H = 0x01;                                                 // Lock register, writing any word other than 0xA5 disables write access to CS-Registers
    //---------------------------------------------------------------------------------------------------------------------------------
   
    RTCCTL1 &= ~RTCHOLD;                                  // Enable RealTimeClock
}

The setup for TimerA is used as follows:

void setup_TA()
{   
    TA0CTL = TASSEL_1 + MC_1;        // CLK_Source = ACLK, Mode = up, ACLK should be set to XT1Clk~32kHz
    TA0CCTL0 = CCIE;                           // Enable Capture Compare Interrupt   
    TA0CCR0 = 82;                                  // Set upper count limit, max 16Bit wakeup ~ each 100 Hz           
}

With Interruptroutine:

#pragma vector=TIMER0_A0_VECTOR
__interrupt void tmra0_isr()
{           
    //LPM4_EXIT;       
    __bic_SR_register_on_exit(LPM3_bits);   
}

Wakeup from interrupt works fine with vlo-clk used as TimerA_source. But vlo-clk stays connected to ACLK even though set to XT1-Clk.

Concerning your Code Greg, I have two questions.

void CS_init(void)

{

     PJSEL0 |= BIT4 + BIT5; // XT1   - -------------------------------------------------------------------------- why setting BIT5 ?--------- Should be don't care ?

     CSCTL0_H = 0xA5;                                            // Unlock register

     CSCTL1 |= DCOFSEL0 + DCOFSEL1;              // Set max. DCO setting

     CSCTL2 = SELA_0 + SELS_3 + SELM_3;      // set ACLK = XT1; MCLK = DCO

     CSCTL3 = DIVA_0 + DIVS_0 + DIVM_0;         // set all dividers 

     CSCTL4 |= XT1DRIVE_0;   ----------------------------------------------------------------------------------- why (CSCTL4  |= 0) -------- should not have any effect on CSCTL4 ?

     CSCTL4 &= ~XT1OFF;
}

It would be nice if someone could help.

Greetings from Berlin.

Helmuth

Hello Helmuth, you are correct, setting BIT5 is not necessary. I misread the table in the datasheet. Setting CSCTL4 |= XT1DRIVE_0; is a bit of redundancy as well. But would indicate 'lowest current consumption for XT1 LF mode'. 

What power mode are you entering and awaiting your TimerA interrupt? If you enter LPM3, ACLK stays active but not LPM4. Also, you can wake up from LPM3.5 using the RTC, but you have not enabled the rtc event interrupt to do so. In LPM4.5, no rtc is possible.

Hi Greg,

thanks for your answer.

The device is currently entering LPM4, it seems as if the command for setting the XT1-CLK does not have any effect and ACLK simply continues to be driven by VLO_CLK at ~8.2kHz. According to Table 3-1 in the datasheet, ACLK is enabled in LPM4 when the ACLKREQEN bit is set in CSCTL6 register. (in my program ACLK seems to be active simply by setting theTIMERA0-source to ACLK without setting the corresponding bit in CSCTL6 register.

The first step I wanted to achieve is to let the wake-up from LPM3 or LPM4 be done by using the XT1-CLK as source for TimerA0 and not the internal VLO-CLK. So ACLK should be running in background to generate the Interrupt.

Later the device should use LPM3.5, and if there is no other solution, I will use the RTC-Interrupts for wake-up.

I would not suggest to initiate your CSCTL4 register like that.

Consider following situation:

CSCTL4  |= XT1DRIVE_3;    // Initially set to 11
CSCTL4  |= XT1DRIVE_0;    // XT1DRIVE is still 11 and not 00  (at least that's what I would assume, might lead to debug-difficulties / hard to find)

Logical 'OR' with 'ZERO' never has any effect to any bit.

Thats true, for the first step of using ACLK <-- XT1CLK and the TIMERA0-Interrupt I did not set any RTC-Interrupts.

Greetings,
Helmuth

Hallo Ralf,

vermutlich hast Du Dein Problem schon gelöst, aber dennoch - auch für das Forum hier - nochmal der Fehler.

Man kann die RTC nicht mit dem Befehl RTCCTL1 &= ~RTCHOLD einschalten. Das RTCCTL1 Register (das Highbyte von RTCCTL01) ist ein 8-Bit Register,
der Wert in RTCHOLD jedoch ein 16-Bit Wert. (siehe auch in der Definition : msp430fr5739.h)

RTCCTL1    &=       ~RTCHOLD
00000000  <---  1011 1111 1111 1111

==>  RTCCTL1 == 1111 1111;

Im Ergebnis ist das RTCHOLD-Bit natürlich ebenfalls Eins und die RTC disabled. (Bytecast)

Grüße,
Helmuth

------------------------------------------------------------------------------------------------------------------------------

To all, enabling RTC does not work using the command RTCCTL1 &= ~RTCHOLD.
The size of RTCCTL1 is 8 bit, the Value stored in RTCHOLD is 16-Bit.

RTCCTL1 &= ~RTCHOLD leads to RTCCTL1 = 1111 1111.

The minimum code needet to initialize a working RTC for the MSP430FR5739 is:

    // First Step:            SETUP RTC-Pins for XT1 Operation  -- set XT1BYPASS-Bit to 0 in CSCTL4 Reg (already preset, so not absolutely necessary)
    PJSEL0 |= BIT4;
    PJSEL1 &= ~BIT4;

   RTCCTL01 &= ~RTCHOLD;        // Enable RTC

Now you can access the RTC-Time-Registers and youd can set any wanted interrupt via the RTCCTL01 register.
There you could eventually use the RTCRDY-Interrupt to get a 1-second interrupt. Having a closer look at page 353
is a good idea if you want to understand the operation of the RTC and the possible interrupts.

The following code shows the isr for RTC-Ready-Interupt and RTC-Oscillator-Fault-Interrupt (any RTC-Interrupt caught):

#pragma vector=RTC_VECTOR
__interrupt void rtc_isr(void)
{
      switch(RTCIV)                                            //RTCIV is self-clearing
      {
          case 0x02 :     // RTCRDY Interrupt
          {
              P2OUT ^= BIT2;              
              break;
          }
       
          case 0x0C:     // Oscillator Fault interrupt
          {            
              P2OUT ^= BIT2;
              break;
          }       
    }           
}

Do not forget to enable interrupts in your main() routine.

__bis_SR_register(GIE);

Greetings,
Helmuth

Hi, 

Thanks for the great information posted here. I have a similar problem; the RTC doesn't run.

I tried the above code but it still not work. The only difference I have is:

I don't have the 12.5pf capacitors , so I only soldered the 32.768k crystal. Does anybody know if the XT1 is still able to work even without the capacitors? Thanks. 

Vincent ZHOU said:

I don't have the 12.5pf capacitors , so I only soldered the 32.768k crystal. Does anybody know if the XT1 is still able to work even without the capacitors? Thanks. 

And for 12.5pF load capacitance, you'll need 2*25pF capacitance on the crystal Minus 2pF processor pin capacitance each and minus any PCB trace stray capacitance. So 2* 22pF to 23pF capacitors are needed for optimum performance.

Thanks, it's very help.

a few more questions for the capacity value:

I checked the user manual(http://www.ti.com/lit/ug/slau343b/slau343b.pdf)  and it lists the C21 and C22 as 12pf;

and then I checked the datasheet(http://www.ti.com/lit/ds/symlink/msp430fr5739.pdf) and it lists different value based on the load:

(a) For XT1DRIVE = {0}, CL,eff ≤ 6 pF.
(b) For XT1DRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
(c) For XT1DRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
(d) For XT1DRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF

1, So the CL,eff means C leg, effective ?

2, based on the user guide, when working with the 32K crystal, the XT1DRIVE means different drive strength. but what that exactly means? for example, in my program, 32K drive the ACK and the RTC. so which number I should choose for the XT1DRIVE?

The XT1 oscillator current can be adjusted to its drive needs.
00b = Lowest current consumption for XT1 LF mode. XT1 oscillator operating
range in HF mode is 4 MHz to 8 MHz.
01b = Increased drive strength for XT1 LF mode. XT1 oscillator operating range
in HF mode is 8 MHz to 16 MHz.
10b = Increased drive capability for XT1 LF mode. XT1 oscillator operating range
in HF mode is 16 MHz to 24 MHz.
11b = Maximum drive capability and maximum current consumption for XT1 LF
mode. XT1 oscillator operating range in HF mode is 24 MHz to 32 MHz

3, what's the consequence if the capacitor value doesn't match the required "drive strength"? the crystal will drift more than claimed 20ppm or the crystal just simple doesn't work? Thanks.

Vincent ZHOU said:

1, So the CL,eff means C leg, effective ?

A crystal is a mechanical resonator (it turns voltage into size change and size change into voltage, so it acts like a mechanical capacitor or inductor, depending on circuitry).
As with any mechanical system, you need some additional power to make it start moving. The more power, the faster it gets moving. After that, you can remove the power to the point where it just compensates the losses.

Driving strength is similar. You might want to set it highest to make the crystal oscillate as quick as possible. Then you may reduce the drive strength to preserve power. But only as much as it still compensates the losses of the circuitry. Which depends on the crystal and the used capacitors. Lower drive strength means lower oscillation voltage and if it is too low, oscillation may cease or may be susceptibel to external influences. It's your job to determine the required minimum setting (or you keep the highest if you don't care for the exter power wasted).

Vincent ZHOU said:

3, what's the consequence if the capacitor value doesn't match the required "drive strength"?

Thanks Jens-Michael,

It's helpful answer!

I just wanted to say thanks for this post, really helped me out.

I have used the followoing part from farnell and soldering by hand was not too bad an ordeal

http://uk.farnell.com/jsp/search/productdetail.jsp?SKU=1740650

Hi, the question may sound stupid but I am just starting to use this board. The RTC needs the XT1 oscillator to operate right? This oscillator should be a 32kHz crystal, is this already on the board or I have to solder it myself?

Thanks

If your refering to the FR5739 expt board, you do have to solder this yourself and you will need the caps. You will have to solder these yourself, its pretty clearly marked where they should go, both on the board and in the manual. the board should come with this crystal in the packaging, but not the caps.

cheers

The crystal is an standard two pin oscillator? And the capacitors aren't standard capacitors, are they? 

Thanks

Julian Mateus said:

The crystal is an standard two pin oscillator?

You can use a standard watch crystal with 32768Hz nominal frequency. I remember a limitation (certain minimum ESR required) from 1x family devices, and there was an appnote about choosing the right crystal.

The capacitors should be low ESR, low tolerance caps and each one must match twice the effective load capacitance (minus 1pF) of the crystal (see its datasheet) to result in best frequency match at room temperature (note that watch crystals have maximum frequency at room temperature, and less above and below)
Ceramic caps with NP0 dielectricum are best.

After reading this thread I became very confused on picking the 2 shunt capacitors (C21 and C22) for the MSP-EXP430FR5739 FRAM Experimenter Board.

Jens, your Sept. statement is different than your Feb. statement. In fact, after reading this TI guide (http://www.ti.com/lit/an/slaa322b/slaa322b.pdf) your Feb. statement is correct and your Sept. isn't. Also, the BOM values and the schematic entry in the User's Guide of the MSP-EXP430FR5739 FRAM Experimenter Board are not correct.

TI supplies a Micro Crystal 32.768 kHz crystal calibrated for a 12.5 pF load capacitance. The shunt capacitance on either side of the crystal should add up to 25 pF for an effective capacitance of 12.5 pF across the crystal. So, given an MSP430FR5739 bond and package capacitance of 2 pF plus let's say 1 pF of PCB trace stray capacitance, we need to populate 22 pF shunt capacitors on each side of the crystal.

C21 and C22 should each be 22 pF, not 12 pF that several people in this thread are using.

Lotus 77 said:

Jens, your Sept. statement is different than your Feb. statement.

Out of curiosity Jens, why is TI using 12 pF caps on either side of the slow clock crystal (CL = 12.5 pF) in their LauchPad eval. boards?

MSP-EXP430F5529LP: http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP-EXP430F5529LP/latest/index_FDS.html Hardware Design Files: (C25, C26)

MSP-EXP430FR5739: http://www.ti.com/lit/pdf/slau343 (C21, C22)

Note: 5529LP link updated by MikeS on 20-Jul-2015

Lotus 77 said:

Out of curiosity Jens, why is TI using 12 pF caps on either side of the slow clock crystal (CL = 12.5 pF) in their LauchPad eval. boards?

For greater good.

When TI populate crystal on board it is easier for anyone that proper load capacitors are there too - so users of board don't need to check documentation of crystal to select right XCAP setting. Not to mention unaware users who simply do not know about XCAP or don't care, in result are getting off-spec oscillator frequency - higher than expected.

Other consideration - XCAP have rough steps. You much more precisely can match load capacitance when use external capacitors.

Lotus 77 said:

I'll rephrase my question, why are 12 pF caps chosen instead of what should be 22 pF caps?

Why you think that 22 pF caps are needed for crystal in question? In case you don't know - every _crystal_ have it's nominal load capacitance. Some need 10pF, some 12pF, some 22 pF and so on.

Lotus 77 said:

I'll rephrase my question, why are 12 pF caps chosen instead of what should be 22 pF caps?

There is no inherent relation between crystal frequency and required load capacitance. Size of the quartz chiplet, cut, angle etc do affect both, (mechanical) frequency and (electrical) capacitance, which must be matched by the load. So don't say "a 32kHz watch quarts requires this load capacitance". only "this specific model of a 32kHz quartz crystal requires this load capacitance"

That could be so, but the crystal that shipped with my FR5739 experimenters board/LaunchPad was labeled CL=12.5pF 

Lotus 77 said:

That could be so, but the crystal that shipped with my FR5739 experimenters board/LaunchPad was labeled CL=12.5pF 

How do you know the soldered caps are 12pF each? How did you measure? (I've never seen a 0806 SMD ceramic cap with any label, and 12pF or 22pF are difficult to separate, especially if soldered)

To be specific, the crystal isn't labeled, but the tape and reel packaging it came in had the CL=12.5 pF label attached. Capacitors were not supplied with the MSP-EXP430FR5739 kit but the users guide for this kit has the schematic and BOM indicating 12 pF shunt caps to be used. I believe the FRAM version of the MSP430 is unique in that it doesn't have selectable internal load caps for external crystals.

Regards

Lotus 77 said:

the users guide for this kit has the schematic and BOM indicating 12 pF shunt caps to be used.

I agree that providing a crystal that needs 12,5pF load (but not telling this) and 12pF mentioned in the schematics would be a real problem.

This is why my schematics usually contain comments to optional configurations. As a reminder for myself as well as for others.

BTW: I just got a schematics for a device based on ATMega128. It didn't include caps for the watch crystal, and the (optional) internal ones are 36pF (=18pF load). A 12pF crystal would be far off. But of course nobody mentioned it in the schematics.