Hi,
The documents and driverlib code seem to conflict a little of ADC clock source options.
Document SLAU445I MSP430FR4xx and MSP430FR2xx family User's Guide
Figure 21-1. ADC Block Diagram shows ADCSHSx selects clock sources:
MODOSC
ACLK
MCLK
SMCLK
Table 21-4. ADCCTL1 Register Description shows
Bit 4-3 ADCSSELx
00b = MODCLK
01b = ACLK
10b = SMCLK
11b = SMCLK
This looks like a typo with SMCLK repeated except document "MSP430 DriverLib for MSP430FR2xx_4xx Devices", for function ADC_init, this has:
void ADC_init ( uint16_t baseAddress, uint16_t sampleHoldSignalSourceSelect, uint8_t clockSourceSelect, uint16_t clockSourceDivider )
where clockSourceSelect options are:
- ADC_CLOCKSOURCE_ADCOSC [Default] - MODOSC 5 MHz oscillator from the clock system
- ADC_CLOCKSOURCE_ACLK - The Auxilary Clock
- ADC_CLOCKSOURCE_SMCLK - The Sub-Master Clock
There is no MCLK option but the ADC_CLOCKSOURCE_SMCLK option is defined as:
#define ADC_CLOCKSOURCE_SMCLK (ADCSSEL_2)
In msp430fr2153.f, this is defined as
#define ADCSSEL_2 (0x0010) /* MCLK */
Note the comment suggests this option is MCLK.
I would just measure it but it would be a bit if a fiddle to get the timings and I have a few other problems, to follow in other posts :) which means my results are not exactly what I would expect so it would be helpful if someone could clear this up.
Regards
Jim Whitehouse
