Different clock frequencies for MCLK SMCLK ACLK

Hi Ven,

I think your intuition must be pretty good.  By default, in UCSCTL4 the setting for ACLK is XT1.  In that case, the XT1LFOFFG flag keeps OFIFG set because XT1 is needed but not oscillating.

Before your do-while loop, if you will set the SELA field to REFO, you should be all set.

Jeff

[Edit: Also SELS_DCOCLK might not be what you want, you might want SELS_DCOCLKDIV.  Either way, you probably want to use the DIVS field in UCSCTL5 to get SMCLK down from 8 or 16 MHz to 1 MHz.]

hi jeff,

thanks for your reply. i've corrected some of the mistakes that you've pointed out (see the following code), and somehow i'm still stuck in the do while loop, as if there's still some sort of fault with the oscillator.

i've configured the SELA to the REFO, SELM to DCOCLK and SELS to the DCOCLKDIV. then i've configured UCSCTL5 as you've asked, by dividing the clock by 8 to have 1MHz from 8MHZ, using the SMCLK source divider DIVS__8. have i forgotten something else or have i done something incorrectly ?

thanks !

VZ

void mcuspeed_mclk_8Mhz_smclk_1Mhz_aclk_32khz (void)

{

SetVCore(PMMCOREV_3);                     // Set VCore = 1.6V for 16MHz clock

  P11SEL |= 0x07;                           // Select P11.0 ACLK, P11.1 MCLK, P11.2 SMCLK

  P11DIR |= 0x07;                           // P11.0 ACLK, P11.0 MCLK,  P11.2 SMCLK set for output

  UCSCTL3 |= SELREF__REFOCLK;                 // Set DCO FLL reference = REFO

  UCSCTL4 |= SELA__REFOCLK;     // Set ACLK = REFO

  UCSCTL4 |= SELM__DCOCLK + SELS__DCOCLKDIV;  // Set MCLK = SMCLK = DCOCLK 

  UCSCTL5 |= DIVS__8; // Set SMCLK = SMCLK/8

  __bis_SR_register(SCG0);                   // Disable the FLL control loop

  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx

  UCSCTL1 = DCORSEL_5;                       // Select DCO range 16MHz operation

  UCSCTL2 = FLLD_1 + 249;                   // Set DCO Multiplier for 8MHz

                                            // (N + 1) * FLLRef = Fdco

                                            // (249 + 1) * 32768 = 8MHz

                                            // Set FLL Div = fDCOCLK/2

  __bic_SR_register(SCG0);                   // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been

  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx

  // UG for optimization.

  // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle

  __delay_cycles(250000);

  // Loop until XT1,XT2 & DCO fault flag is cleared

  do

  {

    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);

                                            // Clear XT2,XT1,DCO fault flags

    SFRIFG1 &= ~OFIFG;                       // Clear fault flags

  } while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

}

Do you have a frequency counter or scope you can use to look at MCLK (true DCOCLK) while that loop executes endlessly?

I don't see anything wrong with your code.  Does it do the same thing if you make this code the contents of main( ).  (Don't forget to disable the watchdog for this test.)

Jeff

Oh, I think I found it.

Ven Zallow said:

  UCSCTL4 |= SELM__DCOCLK + SELS__DCOCLKDIV;  // Set MCLK = SMCLK = DCOCLK 

It's the "|=" curse again.  This just sets more bits, and SELM was already set to DCOCLKDIV.  The final setting of DCOCLK | DCOCLKDIV is 111b, which defaults to XT2 when available (which it is in '5438A).

Try simply setting UCSCTL4 exactly how you want it in one shot, like this:

UCSCTL4 = SELM__DCOCLK + SELS__DCOCLKDIV + SELA__REFOCLK;

Jeff

OFFIFG stays set if any of the OFFG bit s is set. This includes DCO being on lowest or highest setting, or XT2 being enabled but not stuffed with a crystal.
This is a porrible pitfall: even if DCOIFG is initially clear, the FLL might be in the process of rising DCO frequency, finally hitting the uppermost settign without reeachign the desired frequency, and suddenly DCOFFG is set again. Several milliseconds after.
Also, if you do not start the DCO at it lowest setting (and with respect to the adjustment time, tit is better to start it somewhere in the middle, or near a 'usual' final setting based on experience), DCOFFG will be clear bit may be set when the FLL arrives at the upper/under limit without reaching the desirted frequency.

Also, if the FLL is not clocked at all (in your case, it should, as REFOCLK is always on except in LPM4 I think), the FLL willtry to adjust the DCO to n*0 = 0Hz´, eventually reaching the lowest DCO tap and setting DCOFFG.

Then I found some things in the code:

Ven Zallow said:

UCSCTL1 = DCORSEL_5;                       // Select DCO range 16MHz operation

Ven Zallow said:

UCSCTL2 = FLLD_1 + 249;                   // Set DCO Multiplier for 8MHz

Ven Zallow said:

UCSCTL4 |= SELM__DCOCLK + SELS__DCOCLKDIV;  // Set MCLK = SMCLK = DCOCLK 

You simply cannot OR a bitfield into a bitfield if you didn't clear the target bitfield before. OR works bit-wise and not value-wise.
ALL symbols that have an underscore are bitfields and canot be simply ORed.

Ven Zallow said:

// (249 + 1) * 32768 = 8MHz

if your code still stays in the while loop, you shoud set a breakpoint onto the write to UCSCTL7 and check which OFFG bits are set. it might give you a hint which part of the clock system is complaining.

Jens-Michael Gross said:

UCSCTL1 = DCORSEL_5;                       // Select DCO range 16MHz operation

Ven Zallow said:

UCSCTL2 = FLLD_1 + 249;                   // Set DCO Multiplier for 8MHz

However, 8MHz is still in the worst-case range of DCORSEL_5.

[/quote]

The comments are a bit misleading here, but the DCO is truly running at 16MHz.  The multiplier is set for a specific DCOCLKDIV rate (8MHz in this case).

In fact just inserting the word "DCOCLKDIV" before 8MHz in his comment makes it quite a bit clearer what is happening.

Jeff

Ah, I see, it was FLLD_1 and not FLLD__1 :)

Still the multiplier is wrong and gives 16,384MHz

hi,

thanks jens-michael and jeff for your replies. 

well, i've tried your suggestions, namely :

- UCSCTL4 = SELA__REFOCLK + SELM__DCOCLK +SELS__DCOCLKDIV;    (watchdog timer disabled, as usual)

- UCSCTL5 = DIVS__8;  to divide 8MHz to 1MHZ

- FLLD__1 instead of FLLD_1 (i've checked the msp header file, and i've found out that FLLD__1 is valued at 0x0000 whereas FLLD_1 is at 0x1000. so which one does what ?)

when i checked with the oscilloscope, nothing seem to work, not even ACLK which is limited to 32k... even though this time i'm no longer trapped in the do...while loop. 

void mcuspeed_mclk_8Mhz_smclk_1Mhz_aclk_32khz (void)

{

SetVCore(PMMCOREV_3);                     // Set VCore = 1.6V for 16MHz clock

  P11SEL |= 0x07;                           // Select P11.0 ACLK, P11.1 MCLK, P11.2 SMCLK

  P11DIR |= 0x07;                           // P11.0 ACLK, P11.0 MCLK,  P11.2 SMCLK set for output

  UCSCTL3 |= SELREF__REFOCLK;                 // Set DCO FLL reference = REFO

  UCSCTL4 = SELA__REFOCLK + SELM__DCOCLK +SELS__DCOCLKDIV;     // Set ACLK = REFO

  UCSCTL5 |= DIVS__8; // Set SMCLK = SMCLK/8

  __bis_SR_register(SCG0);                   // Disable the FLL control loop

  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx

  UCSCTL1 = DCORSEL_5;                       // Select DCO range 16MHz operation

  UCSCTL2 = FLLD__1 + 249;                   // Set DCO Multiplier for 8MHz

                                            // (N + 1) * FLLRef = Fdco

                                            // (249 + 1) * 32768 = 8MHz

                                            // Set FLL Div = fDCOCLK/2

  __bic_SR_register(SCG0);                   // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been

  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx

  // UG for optimization.

  // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle

  __delay_cycles(250000);

  // Loop until XT1,XT2 & DCO fault flag is cleared

  do

  {

    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);

                                            // Clear XT2,XT1,DCO fault flags

    SFRIFG1 &= ~OFIFG;                       // Clear fault flags

  } while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

}

have i removed the clock entirely by accident ? i've just copied my codes above... the UCSCTL 1 to 5 are all configured accordkingly (at least, i think so)

thanks !

VZ

Ven Zallow said:

(i've checked the msp header file, and i've found out that FLLD__1 is valued at 0x0000 whereas FLLD_1 is at 0x1000. so which one does what ?

My mistake was reading FLLD__1 (/1 divider) and calculating 8MHz while it was instead FLLD_1 whcih is /2 and results in 16MHz DCOCLK (and 8MHz DCOCLKDIV)

FLLD_1 is correct for 16MHz MCLK and 8MHz (/8) SMCLK.

Ven Zallow said:

when i checked with the oscilloscope, nothing seem to work, not even ACLK which is limited to 32k

Ven Zallow said:

i'm no longer trapped in the do...while loop. 

So your clocking configuration is probably working now.  (Although as JMG said you want to use FLLD_1, or in your case, the equivalent FLLD__2 might read better with all your other uses of the double underscore.  By using FLLD__1, you have configured DCOCLK = DCOCLKDIV = 8MHz, which works but isn't what you wanted.)

If you're not seeing anything on the scope, that's a new problem.  Either the scope isn't configured properly or the MSP430 isn't running any clocks when you look.  Do you use any low-power modes?

Jeff

Dear all,

I'm trying to configure my MSP430F435IPZ to use the MCLK for the CPU, SMCLK for peripherals. I'm using an external xtal of 32768Hz for ACLK.

the idea it to keep the hole thing as "low power" as possible. So I use LPM3. I've also noticed one can select the ALCK or SMCLK for each peripheral. Is this for each peripheral default OFF? because there are some peripherals which I don't use at all.

Here is the code of how I configured the whole thing right now, I read the entire info about the FLL+ etc, but I'm still not sure if the following code is correct:

void Configure_Clocks(void)
{
unsigned int i;

//3 CLOCKS:
// MCLK Master Clock: is used by the CPU and system
// SMCLK Sub system Master Clock: is software selectable for individual peripheral modules.
// ACLK Aux Clock: The ACLK is software selectable as LFXT1CLK or VLOCLK as clock source. ACLK is software selectable for individual peripheral modules.
// No VLO present

//Configure ACLK 32765Hz XTAL
// FLL_CTL0 FLL+ control register 0:
// Setting the internal DCO to run at 2.45MHz with auto-calibration by the FLL+ circuitry.
// ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO = (74+1) x ACLK = 2457600Hz
//FLLD0 = 0, FLL+ Loop divider /1
//FN_2 = 001x
//MOD0 = 0, modulator LSB
SCFI0 |= FN_2; // x2 DCO, 4MHz nominal DCO
SCFQCTL = 74; // (74+1) x 32768 = 2.45Mhz & modulation enabled

// DCOPLUs = 0x00: DCO output is divided
// XTS_FLL = 0: 32765Hz in Low Freq mode
// XCAPxPF = 01 (OSCCAP_1); 6pF Load Capacitance
// XT2OF = 0x00 XT2, No fault condition present
// XT1OF = 0x00 LFXT1 HF, No fault condition present
// LFOF = 0x00 LFXT1 LF, No fault condition present
// DCOF = 0x00 DCO, No fault condition present
FLL_CTL0 |= OSCCAP_1; // Configure load caps

//FLL_CTL1 FLL+ control register 1:
// LFXT1DIG = Not supported by cpu
// SMCLKOFF = 0x00 Sub System Clk ON
// XT2OFF = High Frequency Oscillator 2 (XT2) disable
// SELMx = SELM_DCO = Select DCO for CPU MCLK
// SELS = 0x00 DCOCLK selected
// FLL_DIVx = FLL_DIV_1 = /1
FLL_CTL1 |= SELM_DCO + XT2OFF + FLL_DIV_1;

// Delay for 32 kHz crystal to stabilize
for(i=0;i<10000;i++);

//Configure Timer_A
TACCTL0 = CCIE; // Timer_A capture/compare control 0: CCR0 interrupt enabled
TACCR0 = (32768-1);///2; //500ms //Timer_A capture/compare 0
TACTL = TASSEL_1 + MC_1; // Timer_A control: ACLK, up mode
}

Anonymous said:

I'm trying to configure my MSP430F435IPZ to use the MCLK for the CPU

Anonymous said:

I've also noticed one can select the ALCK or SMCLK for each peripheral. Is this for each peripheral default OFF?

Anonymous said:

FLL_CTL0 |= OSCCAP_1; // Configure load caps

Anonymous said:

// Delay for 32 kHz crystal to stabilize
for(i=0;i<10000;i++);

After the crystal has stabilized, the FLL can adjust DCO to the desired frequency. It may take up to 1000 XT1 cycles until th FLL has settled (worst case). You can use the timer for counting ACLK and therefore XT1 pulses.

Afte rthis time, and when DCOF is still clear (if not, your FN_x settign doesn't fit the requested freuency), then the frequencies have stabilized.

Keep in mind that entering any LPM above LPM0 will disable the DCO and therefore interferes with the FLL adjustment. o after waking from any LPm that ahs disabled the DCO, the FLL mus tbe given time to stabilize the DCO again. It surely will only take a few XT1 ticks, bu tyou cannot assume the DCO frequency being stable after LPM. (except for LPM0 which doesn't disable the DCO)

Anonymous said:

TACCTL0 = CCIE; // Timer_A capture/compare control 0: CCR0 interrupt enabled

Anonymous said:

TACCR0 = (32768-1);///2; //500ms //Timer_A capture/compare 0

Hi Jens-Michael,

Thanks for your reply,

Jens-Michael Gross said:

You surely will eb successful here, since MCLK is the only clock source available for the CPU. And it is the default clock too. So you simply cannot change anything here. MCLK is and will ever be clocking the CPU :)

Ok, maybe I was a little bit to fast with posting, what I meant offcourse was: The CPU has indeed only MCLK. But how do I successfully configure MCLK from XT1.

I figured out how to set it on a certain freq:

//Configure ACLK 32765Hz XTAL
// FLL_CTL0 FLL+ control register 0:
// Setting the internal DCO to run at 2.45MHz with auto-calibration by the FLL+ circuitry.
// ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO = (74+1) x ACLK = 2457600Hz
//FLLD0 = 0, FLL+ Loop divider /1
//FN_2 = 001x
//MOD0 = 0, modulator LSB
SCFI0 |= FN_2; // x2 DCO, 4MHz nominal DCO
SCFQCTL = 74; // (74+1) x 32768 = 2.45Mhz & modulation enabled

// DCOPLUs = 0x00: DCO output is divided
// XTS_FLL = 0: 32765Hz in Low Freq mode
// XCAPxPF = 01 (OSCCAP_1); 6pF Load Capacitance
// XT2OF = 0x00 XT2, No fault condition present
// XT1OF = 0x00 LFXT1 HF, No fault condition present
// LFOF = 0x00 LFXT1 LF, No fault condition present
// DCOF = 0x00 DCO, No fault condition present
FLL_CTL0 |= OSCCAP_1; // Configure load caps

//FLL_CTL1 FLL+ control register 1:
// LFXT1DIG = Not supported by cpu
// SMCLKOFF = 0x00 Sub System Clk ON
// XT2OFF = High Frequency Oscillator 2 (XT2) disable
// SELMx = SELM_DCO = Select DCO for CPU MCLK
// SELS = 0x00 DCOCLK selected
// FLL_DIVx = FLL_DIV_1 = /1
FLL_CTL1 |= SELM_DCO + XT2OFF + FLL_DIV_1;

On page 5-4 of the "MSP430x4xx Users Guide" one can see one can select which clock will be used for MCLK using SELMx. In this case I will use the DCO as shown in the code above.

Anonymous said:

I've also noticed one can select the ALCK or SMCLK for each peripheral. Is this for each peripheral default OFF?

Jens-Michael Gross said:

Many peripherals have an 'extern clock' or othe rperipheral-psecific clock option beside SMCLK and ACLK. Usually, this is the default then. However, modules only 'request' the clock if they need it. Disabled modules do not request a clock at all, independently of the selection made in the module.

I suppose in a low power controller, the peripherals are default OFF? (maybe it's a stupid question, but it's the first time I'm working with an MSP)

Anonymous said:

FLL_CTL0 |= OSCCAP_1; // Configure load caps

Jens-Michael Gross said:

is 6pF the required load capacitance for your watch crystal on XT1?

Yes, that's what the datasheet of the xtal says.

Jens-Michael Gross said:

This is wishful thinking. You don't know whether the crystal will operate at all. Also, a simple for-loop wihtout any volatile content, will be optimized away by the compiler as it 'does nothing'. (The compiler doesn't know that 'doing nothing for some time' is your intention).

You'll have to clear teh OF bits in FLL_CTL0, clear teh OFIFG flag in IFG1 then wait for some time and repeat the loop if OFIFG is set again. It may take hundreds of milliseconds before the crystal is stabilized. If at all (wrong load capacitance or other problems).

After the crystal has stabilized, the FLL can adjust DCO to the desired frequency. It may take up to 1000 XT1 cycles until th FLL has settled (worst case). You can use the timer for counting ACLK and therefore XT1 pulses.

Afte rthis time, and when DCOF is still clear (if not, your FN_x settign doesn't fit the requested freuency), then the frequencies have stabilized.

Keep in mind that entering any LPM above LPM0 will disable the DCO and therefore interferes with the FLL adjustment. o after waking from any LPm that ahs disabled the DCO, the FLL mus tbe given time to stabilize the DCO again. It surely will only take a few XT1 ticks, bu tyou cannot assume the DCO frequency being stable after LPM. (except for LPM0 which doesn't disable the DCO)

Thanks, I will give it a shot :)

Anonymous said:

TACCTL0 = CCIE; // Timer_A capture/compare control 0: CCR0 interrupt enabled

Jens-Michael Gross said:

You should clear any already pending CCIFG bit or this migh tcause an erroneous ISR call as soon as GIE is set.
Do you have an ISR for TIMER0_A0_VECTOR? If not, you'll experience a reset when TAR counts to TACCR0.

Anonymous said:

TACCR0 = (32768-1);///2; //500ms //Timer_A capture/compare 0

Jens-Michael Gross said:

On 32768Hz ACLK, this gives 1s intervals, not 500ms.

This was still a quick debug test: it must offcourse be /2.

Yes I have a interrupt timer routine:

// Timer A0 interrupt service routine
// Refresh LCD by reading framebuffer every x ms
#pragma vector=TIMERA0_VECTOR
__interrupt void Timer_A (void)
{
LED1_TOGGLE;
LCD_Read_FrameBuffer(); // this is placed in the timer routine because of moving segments on the LCD
}

Anonymous said:

But how do I successfully configure MCLK from XT1.

First, you msu thave XT1 up and running. This means, the apropriate falut flag must be clear (this depends on teh clock module which is different for each processor family), and then you can change the MSEL setting to switch MCLK from DCO to XT1. If XT1 fails, MCLK will automatically switch back to DCO. You may want to set up an NMI ISR to catch the OSC fault event (indicatign that one of the oscillators has failed and if uit is XT1, MCLK ha sbeen switched byck toDCO already)

Anonymous said:

I suppose in a low power controller, the peripherals are default OFF?

Anonymous said:

LCD_Read_FrameBuffer(); // this is placed in the timer routine because of moving segments on the LCD

So this thread has helped out a good bit in understanding how to configure the FLL and clocks on a bigger MSP like the ones discussed above.  I've got some simple sanity check questions though just because I want to make sure I understand these concepts.  You basically pick a reference clock like REFOCLK and then set the value you want to multiply it by in the FLLNx bits in the UCSCTL2 register?  You can then divide the reference clock coming in and the DCO output going out?  In working with this with a scope I noticed that it doesn't seem like the FLL modifies the DCORSEL bits so this must be done manually? 

Also, in looking at this on a scope it seems very inaccurate when I measure a period.  I realize this isn't a PLL, but an FLL and it sounds like it is similar to the DCO in that it is an average of periods that will yield the target period.  Is this correct?  I'm measure up to a megahertz off when I try to tune it.  Is that normal? 

Thanks,

Rob

Robbie Valentine said:

You basically pick a reference clock like REFOCLK and then set the value you want to multiply it by in the FLLNx bits in the UCSCTL2 register?

Robbie Valentine said:

You can then divide the reference clock coming in and the DCO output going out?

In addition, you can divide the reference input (FLLREFDIV). This allows you to use a higher multiplier for the target frequency. For a 32768Hz reference, the multiplier for 1MHz tagrget frequenc would be 30.5. But you can pick only 30 or 31. By using 16384 Hz as reference, the multiplier for 1MHz would be 61. Mor precise target frequency selection at the cost of a slower update cycle.

Robbie Valentine said:

it doesn't seem like the FLL modifies the DCORSEL bits so this must be done manually? 

Robbie Valentine said:

I realize this isn't a PLL, but an FLL and it sounds like it is similar to the DCO in that it is an average of periods that will yield the target period.  Is this correct?

Well, on >8MHz, 12% jitter can be indeed a change of 1MHz between two clock pulses. See above for using DCOCLKDIV and overclocking the DCO in order to reduce this jitter.