MSP430FR5994: Configuring Timer B0.4 interrupt vector

void init_TB0_4()
{
    P1DIR &= ~BIT7;                                                 // Set P1.7 as an input
    P1SEL0 |= BIT7;                                                 // Select Timer_B function for P1.7
    P1SEL1 &= ~BIT7;

    TB0CTL = TBSSEL__SMCLK | MC__CONTINOUS | TBIE | ID_1 | TBCLR;   // Set Timer B0 clock source to system clock enable timer B interrupt
    TB0CCTL4 = CAP | CM_1 | CCIS_1 | SCS_1;                         // Configure Timer B0.4 CAPture mode. Rising edge. CCIxB. Synchronous capture
}

#pragma vector = TIMER0_B1_VECTOR
__interrupt void Timer0_B1_ISR(void)

{
  switch(__even_in_range(TB0IV,TB0IV_TB0IFG))//
       {
           case TB0IV_TB0CCR4:

               //FCount[Fpoint++] = TA1CCR1;

               if (TB0CCR4 < LastVal)
               {
                   Overflow += 0x10000;
               }

               FCount[Fpoint++] = TB0CCR4 + Overflow;
               LastVal = TB0CCR4;

               if (Fpoint >=64)
               {
                   TB0CCTL4 &= ~CCIE;
                   Freq = (FCount[63] - FCount[0])>>6;
                   splitUint16(Freq, &f_msb, &f_lsb);               // Split 16bit Freq into two 8bit numbers
                   UART_TXBuffer[0] = f_msb;                        // Element 0 of UART_TXBuffer array hold frequency count msb
                   UART_TXBuffer[1] = f_lsb;                        // Element 1 of UART_TXBuffer array hold frequency count lsb
                   TXbyte = 0;                                      // Initialise TXbyte
                   TX_Data_Len = 2;                                 // Number of bytes to be sent
                   UCA1TXBUF = UART_TXBuffer[TXbyte++];             // Transmit the first byte from UART_TXBuffer array
                   Fpoint = 0;
                   LastVal = 0;

                   //for(clrFCount=0; clrFCount<32; clrFCount++)
                   //{
                   //FCount[clrFCount] = 0;
                   //}
               }
               break;

           case TB0IV_TBIFG:
               break;

           default: break;
       }
}