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Interrupt Vectors A3 Timer

Silver Diamond
Genius 4010 points
Other Parts Discussed in Thread: MSP430FR5739

Having hard time tying thing together.  According to the SPEC SHEET MSP430fr5739.pdf, TA0 has two vectors TA0-TA0CCR0 is 0FFEAh and the TA0-TA0IV is 0FFE8h but according to MSP430FR57xx family guide, timer A3 has the following vectors:

The other section talks about the TAxCCRO CCIFG flag as below

The msp430fr5739.h defines two vectors:

1) TA0CCR0=> 0FFEAh which is TIMER0_A0_VECTOR

2) TA0IV =>0FFE8h which is TIMER0_A1_VECTOR.

So the question is, looking at the family guide, I understand the TA0IV and how to use it, but where does the TA0CCR0 come from and how do you enable it, which bit do I use in ISR defenition?

  • 0
    Guru 227245 points

    Silver Diamond said:
    according to MSP430FR57xx family guide, timer A3 has the following vectors:

    These ar ento vectors, these are the registers the timer can have. (not all timers implement all seven CCR units).

    Each of the CCXy/CCTLx pairs is a possible interrupt source, as well as the timer itself (timer overlfow). All but the CCR0/CCTL0 interrupt trigger all the same ISR, TIMERx_A1_vector. Only CCR0/CCTL0 triggers the TIMERx_A0_VECTOR ISR. THis one also auto-clears the CCIFG bit in CCTL0 register. (there is only one interrupt source and since you entered the ISR, it is handled and cna be cleared). All other ISR bits must be cleared inside the ISR once handled.

    You may also read the TAxIV register (not an interrupt vecto but an vector generator register). It will on each read retuen a value that represents the highest pending interrupt of Timer Ax (except the CCR0 one) and will at the same time clear the associated IFG bit.

    Other hardware modules have a similar IV register.

    Silver Diamond said:
    but where does the TA0CCR0 come from and how do you enable it

    It is enbaled the same way as all others:by setting the CCIE bit in CCTL0 register. It just triggers a different ISR than all others (and therefore isn't handled by the IV register).
    CCR0/CCTL0 is a bit special because in tiem rup mode it handles the tiemr overflow. So it got its own ISR 'shortcut' to speed up its handling.

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