MSP430 Timer Interrupt Vector Register Programming

Michael Choi said:

First Question:

     If two, or more, enabled pending interrupts arise simultaneously, is it only possible to see one, and only one, interrupt number in the Timer Interrupt Vector register at any point in time?

You can only see the interrupt being granted in the TxIV register. Pending interrupts are not visible in TxIV.

Michael Choi said:

Second Question:

     In terms of reading the contents of the TAIV register (or the TBIV) register for processing by an interrupt handler, can anyone show me a code snippet that is the fastest way to transfer data from the timer interrupt vector register?

The assembly code shown in the User's Guide is most efficient. c-code such as switch (_ _even_in_range(TAIV, 10)) is not bad either.

Michael Choi said:

I was considering moving data from the interrupt vector register to a general purpose register, or a memory location, for processing however, does a faster, direct method, exist?  A code snippet would be the most helpful.

TxIV is volatile, copy it to anywhere else does not seem to make sense.

Dear Old_Cow_Yellow;

      Thank  you for your informative reply.   You answered my question.

       Your excellent reply was appreciated. 

       Sincere Regards,

       Thank you, again.

OCY, that’s not strictly true. ‘granted’ is not the right term here.
The IV register always shows the highest pending (IFG) and enabled (IE) interrupt. But
1) interrupts may clear before you read the IV register, in which case it may report 0,
2) you may read the IV register while interrupts are globally disabled, in which case you’ll still get the highest pending and enabled interrupt, even though no interrupt was granted,
3) reading the IV register clears the highest pending and enabled interrupt, but if two were pending and enabled, its next read will return the next one, even though no second interrupt was ‘granted’ so far.
In fact, because of 3), it is recommended to put the switch statement that reads the IV register into a while(1) loop and exit the ISR for case 0. This saves the ISR entry and exit code, handling all pending interrupts in a row.