• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 79 subscribers
  • Views 121 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

MSP430FR5869: MSP430 GPIO reset after enter into bsl

MSP430FR4133: MSP430FR4133

Ankush jain
Prodigy 10 points
Part Number: MSP430FR4133

MCU: MSP430FR4133.
1) Application code is executing & set P8.3 pin state is output high state.
2) MSP430FR4133 enters in the BSL (Boot Strap Loader) mode via the BSL entry sequence set on the RST and TEST pins.
During this transition to BSL mode, do the states of all GPIO pins, including P8.3, remain locked or preserved in the same state they were in before entering BSL mode?

  • 0
    TI__Expert 5082 points

    Hi, 

    GPIO is in default mode druing BSL (uninitialized state).

    Regards,

    Helic

  • 0 in reply to Helic Chi
    Prodigy 20 points

    Hi Helic Chi,

    As per www.ti.com/.../slau445i.pdf

    "

    During LPMx.5 the I/O pin states are held and locked based on the settings before LPMx.5 entry. Note
    that only the pin conditions are retained. All other port configuration register settings such as PxDIR,
    PxREN, PxOUT, PxIES, and PxIE contents are lost.
    Upon exit from LPMx.5, all peripheral registers are set to their default conditions but the I/O pins remain
    locked while LOCKLPM5 remains set. Keeping the I/O pins locked ensures that all pin conditions remain
    stable when entering the active mode, regardless of the default I/O register settings.
    When back in active mode, the I/O configuration and I/O interrupt configuration such as PxDIR, PxREN,
    PxOUT, and PxIES should be restored to the values before entering LPMx.5. The LOCKLPM5 bit can
    then be cleared, which releases the I/O pin conditions and I/O interrupt configuration. Any changes to the
    port configuration registers while LOCKLPM5 is set have no effect on the I/O pins.
    After enabling the I/O interrupts by configuring PxIE, the I/O interrupt that caused the wakeup can be
    serviced as indicated by the PxIFG flags. These flags can be used directly, or the corresponding PxIV
    register may be used. Note that the PxIFG flag cannot be cleared until the LOCKLPM5 bit has been
    cleared.

    "

    Does this mean that If I am in LPMx.5 before entering the BSL mode then I can retain the pin's state?

  • 0 in reply to Rajan Kumar
    Prodigy 10 points

    Hi Rajan,

    1. When the MSP430Fr4133 is in Boot Strap Loader (BSL) mode:
      • Specific input/output (I/O) configurations are mandated by the BSL mode to facilitate data transmission and reception on the UART channel.
      • These configurations are essential for proper operation of the UART communication.
    2. Not all GPIO pins may be uniformly locked:
      • Some GPIO pins may have their states locked according to BSL mode requirements.
      • Other GPIO pins might revert to their default mode or may lock its state as per LOCKLPM5. 

    So, I think, it’s not possible to lock all GPIO pin state in BSL mode.

  • 0 in reply to Ankush jain
    TI__Expert 5082 points

    Hi,  and 

    For LPMx.5, this is about switching between LPM and run mode.

    For BSL, BSL entry requires a Reset and Test pin signal. Any user application code can not influence to BSL GPIO status.

    If device support user defined BSL code, we can modify GPIO, but there is still a period of reset condition.

    Regards,

    Helic

**Attention** This is a public forum