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What does ACLK and SMCLK source?

Other Parts Discussed in Thread: MSP430F6638

Hi, I'm new to MSP430F6638..  I fully understand how to configure the UCS and that MCLK sources the CPU, but what does ACLK and SMCLK source? Moreover, if they both source all same modules is the usefullnes of the multiple clks for low power usage?.... Thanks....

  • Hi,

    all MSP430 controllers work with usually three clock sources (MCLK, SMCLK, and ACLK).

    MCLK is used as clock source for the CPU.

    SMCLK is usually a high frequency clock and it is used for peripheral modules (e.g. Timers, serial communication modules, ...)

    ACLK is usually a 32kHz crystal clock. It is used for peripheral modules that require a low-frequency clock (e.g. real-time-clock,  ...)

    Your estimation about low-power modes is correct. The different low-power modes of MSP430 is basically an operation with different clock sources active. Active mode means, that MCLK, SMCLK, ACLK are running. In LPM3 mode - most often used in applications to reduce current - MCLK, SMCLK and all high-frequency oscillators are off and only ACLK (32kHz crystal oscillator) is on.

    The usage of ACLK and SMCLK depends on your application. In most cases you want to implement either an real-time clock or a timer that wakes-up the CPU after a long time. Clocking a timer with 32kHz helps here.

    Especially since the MSP430 is a CMOS design the current consumption of the digital parts are caused by clock edges (static levels will not cause current in a CMOS desing - assume that leakage doesn't matter). Reducing the edges in the MCU will also reduce the current consumption of the controller. So 32kHz operation compared with 1MHz or higher will definitely have a benefit regarding to current consumption....

    Regards.

  • Thank you....

  • Voyager said:

    Hi,

    all MSP430 controllers work with usually three clock sources (MCLK, SMCLK, and ACLK).

    MCLK is used as clock source for the CPU.

    SMCLK is usually a high frequency clock and it is used for peripheral modules (e.g. Timers, serial communication modules, ...)

    ACLK is usually a 32kHz crystal clock. It is used for peripheral modules that require a low-frequency clock (e.g. real-time-clock,  ...)

    Your estimation about low-power modes is correct. The different low-power modes of MSP430 is basically an operation with different clock sources active. Active mode means, that MCLK, SMCLK, ACLK are running. In LPM3 mode - most often used in applications to reduce current - MCLK, SMCLK and all high-frequency oscillators are off and only ACLK (32kHz crystal oscillator) is on.

    The usage of ACLK and SMCLK depends on your application. In most cases you want to implement either an real-time clock or a timer that wakes-up the CPU after a long time. Clocking a timer with 32kHz helps here.

    Especially since the MSP430 is a CMOS design the current consumption of the digital parts are caused by clock edges (static levels will not cause current in a CMOS desing - assume that leakage doesn't matter). Reducing the edges in the MCU will also reduce the current consumption of the controller. So 32kHz operation compared with 1MHz or higher will definitely have a benefit regarding to current consumption....

    Regards.

    Good to know! Also page 12 of MSP430F471X3,X6,X7 has good knowledge about the LPM and AM as well.

  • Voyager said:

    Great explanation...really helpful 

  • Voyager said:
    SMCLK is usually a high frequency clock and it is used for peripheral modules (e.g. Timers, serial communication modules, ...)

    ACLK is usually a 32kHz crystal clock. It is used for peripheral modules that require a low-frequency clock (e.g. real-time-clock,  ...)

    While this is correct, there's more about this.

    The name "SMCLK" stands for "Sub-Main CLocK". It is usually assumed, that SMCLK and MCLK are synchronous (derived from the same oscillation source) and SMCLK is an integral fraction of MCLK. Peripherals driven by SMCLK can be accessed by the CPU without racing conditions on hardware level.
    ACLK (Auxiliary CLocK) is assumed to be independent form MCLK. When a peripheral is driven by ACLK, an ALCk tick may happen right in the middle of an MCLK cycle, causing problems (see notes about reading the timer register TAR when TACLK is not synchronous to MCLK)

    On older device families, the design of the clock module supported this (e.g. only ACLK could be driven by LF crystal) On 5x family, however, ACLK and SMCLK are mostly exchangeable. Except for the deactivation order in LPM3 and LPM4. And the default configuration (SMCLK=DCO, ACLK=REFO/LFXT1).

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